DS3105DK Maxim Integrated Products, DS3105DK Datasheet - Page 8

• Manufacturer Part Number: DS3105DK
• Description: Power Management Modules & Development Tools Demo Kit for DS3105 Demo Kit for DS3105
• Manufacturer: Maxim Integrated Products

Specifications of DS3105DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.
Figure 4-1. Software Main Screen
4.1
In the upper-left corner of the main window are several global status and configuration fields. The ID field displays
the device part number and revision. The PORT field shows the COM port to which the DK board is connected.
The DEMO MODE checkbox, which is checked by default, must be unchecked to enable the software to
communicate with the DK board. The ENABLE POLLING checkbox, also checked by default, controls software
polling of the device. The RESET checkbox controls MCR1:RESET in the device. Finally, the SDH and SONET
radio buttons (which control device register field MCR3:SONSDH) specify whether 1.544MHz (SON) or 2.048MHz
(SDH) is an available frequency option for the input clocks.
4.2
This box occupying the left-center section of the main window contains the most frequently used configuration and
status associated with input clocks IC3–IC6. Note that the device does not have an IC7 input clock.
Just to the right of the input clock numbers (3, 4, 5, 6, and 9) are software LEDs that indicate the state of each input
as reported by its input monitor. These LEDs are red in the absence of any other condition. When a clock of the
correct frequency is applied to an input, the associated LED turns green when activity is detected. If an input is
disqualified by one of the DPLLs because the DPLL could not lock to it, the LED turns magenta.
In the middle of the box, the FREQ and LK MODE fields configure the frequency and lock mode (direct-lock, DIVN,
LOCK8K, or alternate direct-lock) for each input clock. At the bottom is a field to configure the DIVN divider used
for inputs configured for DIVN mode.
All the fields in the box containing the PRIORITY fields display information about either the T0 DPLL or the T4
DPLL, depending on which of two radio buttons is selected at the top of the box. The PRIORITY fields configure
the input clock priorities for the selected DPLL (1 highest, 15 lowest, 0 disabled). The SEL REF field shows the
Rev: 012808
_________________________________________________________________________________________DS3105DK
Overview of the Software Interface
Global Configuration
Input Clock Monitor, Divider, and Selector
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