DS3105DK Maxim Integrated Products, DS3105DK Datasheet - Page 14

• Manufacturer Part Number: DS3105DK
• Description: Power Management Modules & Development Tools Demo Kit for DS3105 Demo Kit for DS3105
• Manufacturer: Maxim Integrated Products

Specifications of DS3105DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.8
The DPLL frequency limits specify the hard and soft limits of the DPLL frequency range. When the selected
reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is
not disqualified. If the FLLOL (frequency limit loss of lock) box is checked in the DPLL LOCK CRITERIA box,
when the selected reference for a DPLL exceeds the hard limit the DPLL will lose lock (T4 transitions to Not Locked
state, and T0 transitions to LOL state).
The remaining fields are advanced topics. See
Table 4-7. Mapping Between DPLL Software Fields and DS3105 Register Fields
4.9
Any known frequency error in the local oscillator can be calibrated out inside the DS3105 by setting the ppm value
in the REFCLK CAL box. Also, the significant edge of the REFCLK signal can be selected in XOEDGE field.
Table 4-8. Mapping Between REFCLK Software Fields and DS3105 Register Fields
4.10 Programmable DFS
When the Programmable DFS button in the upper-right corner of the main window is pressed, the Programmable
DFS window appears
configured to synthesize a custom frequency that is a multiple of 2kHz (f < 77.76MHz), a multiple of 8kHz (f ≤
311.04MHz), or a multiple of 10kHz (f < 388.79MHz). The desired frequency can be entered in the Target Output
Clock Frequency (MHz) box at the top of the window, and the software then performs the necessary computations
to fill in the other numerical fields in window.
The programmable DFS configuration can be applied to one or more DFS engines as specified in the Use
Programmable DFS box. Frequencies below 77.76MHz are typically synthesized by the DIG1 or DIG2 DFS
engine and brought out on CMOS/TTL output clock pin(s) by selecting DIG1 or DIG2 in the appropriate output
clock configuration field in the main window of the software. Frequencies of 77.76MHz or above must be
synthesized using an APLL DFS and its associated APLL, and are typically brought out on differential output clock
pin(s).
If a group of custom clock rates that are related to one another by factors of 1, 2, 4, 6, 8, 10, 12, 16, 20, 48, or 64
are needed, often the highest frequency clock can be produced through one of the APLL DFS blocks and then
various lower rate clocks can be selected on one or more of the output pins. Refer to the OCR2 and OCR3
registers in the DS3105 data sheet for details.
Rev: 012808
_________________________________________________________________________________________DS3105DK
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
REFCLK Calibration
REFCLK slider/text box
SOFTWARE FIELD
SOFTWARE FIELD
COURSELIM
HARD LIMIT
SOFT LIMIT
USEMCPD
MCPDEN
XOEDGE
FINELIM
(Figure
NALOL
FLLOL
CLEN
FLEN
D180
4-5). In this window one or more of the output DFS engines in the DS3105 can be
Table 4-7
and the DS3105 data sheet for more details.
MCLKFREQ[15:0] in MCLK1 and MCLK2
HARDLIM[9:0] in DLIMIT1 and DLIMIT2
DS3105 REGISTER FIELDS
DS3105 REGISTER FIELDS
PHLIM2:COARSELIM
PHLIM2:USEMCPD
DLIMIT3:SOFTLIM
PHLIM2:MCPDEN
PHLIM1:FINELIM
MCR3:XOEDGE
DLIMIT3:FLLOL
PHLIM1:NALOL
PHLIM2:CLEN
PHLIM1:FLEN
TEST1:D180
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