DS3105DK Maxim Integrated Products, DS3105DK Datasheet - Page 11

• Manufacturer Part Number: DS3105DK
• Description: Power Management Modules & Development Tools Demo Kit for DS3105 Demo Kit for DS3105
• Manufacturer: Maxim Integrated Products

Specifications of DS3105DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-2. Mapping Between T0 DPLL Software Fields and DS3105 Register Fields
4.4
In the DS3105, the T4 DPLL can only be used for measuring frequency and phase of input clocks. It is not a clock
source for the T4 APLL or any other output clock logic. The T4 APLL is slaved to the T0 DPLL in the DS3105.
The state of the T4 DPLL (locked or not locked) is shown in the STATE field. The LOCK button represents a
latched status bit in the device. When the button is red, the corresponding latched status bit has been set in the
DS3105. Pressing the button clears the latched status bit and changes the color of the button back to green. LOCK
indicates that the state of the T4 DPLL has changed since the last time the button was pressed. The selected
reference for the T4 DPLL can be forced using the CLK SEL field.
The bandwidth of the T4 DPLL is set by the BW field, while the damping factor is set by the DAMP field. If the
frequency of the T4 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY
LIMITS box at the top of the window), the SOFTLIM LED turns red.
Rev: 012808
_________________________________________________________________________________________DS3105DK
MAIN WINDOW
SUBWINDOW
T4 DPLL
PHASE DETECTOR 2 Enable
STATE latched status button
APBO OFFSET (ns)
SOFTWARE FIELD
Revertive/Non-Rev.
MANUAL PBO (ns)
STATE combo box
STATE status box
Freerun Holdover
SYNC2K Mode
SYNC1 Source
SYNC2 Source
SYNC3 Source
Holdover Type
SYNC1 Phase
SYNC2 Phase
SYNC3 Phase
HO Ready
SOFTLIM
AUTOBW
CLK SEL
PALARM
PBOFRZ
MONLIM
AEFSEN
PD2G8K
FSMON
SRFAIL
PBOEN
RECAL
EFSEN
LIMINT
INDEP
DAMP
FREQ
PD2G
ABW
OCN
LBW
Derived by software from SYNC2K Mode
Derived by software from SYNC2K Mode
Derived by software from SYNC2K Mode
FSCR3:SOURCE, FSCR1:SYNCSRC
Fixed by T0 DPLL architecture
DS3105 REGISTER FIELDS
OFFSET1 and OFFSET2
OPSTATE:T0STATE
OPSTATE:T0SOFT
OPSTATE:FSMON
MCR2:T0FORCE
MCR10:PBOFRZ
VALSR2:HORDY
FSCR3:MONLIM
MCR1:T0STATE
TEST1:PALARM
MCR9:AUTOBW
FSCR2:PHASE1
FSCR2:PHASE2
FSCR2:PHASE3
MCR3:FRUNHO
T0CR2:PD2G8K
MCR3:REVERT
MCR10:PBOEN
MCR3:AEFSEN
FSCR3:RECAL
T0CR3:PD2EN
MSR2:SRFAIL
FSCR2:INDEP
MCR3:EFSEN
T0CR2:DAMP
MCR9:LIMINT
MSR2:STATE
T0CR3:PD2G
HOCR3:AVG
FSCR2:OCN
T0ABW
T0LBW
PBOFF
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