HV9112DB3 Supertex, HV9112DB3 Datasheet - Page 5

• Manufacturer Part Number: HV9112DB3
• Description: Power Management Modules & Development Tools HV9112 Demo Brd
• Manufacturer: Supertex

Specifications of HV9112DB3

• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Test Circuits
Detailed Description
Preregulator
The preregulator/startup circuit for the HV9112 consists of
a high-voltage n-channel depletion-mode DMOS transis-
tor driven by an error amplifier to form a variable current
path between the VIN terminal and the VDD terminal. The
maximum current (about 20 mA) occurs when V
current reducing as V
when V
if V
supply the chip is controlling). No current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
C
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor V
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
STORAGE
DD
+10V
(V
is held at 10 or 12V by an external source(generally the
(–V
GND
DD
NOTE:
DD
(FB)
IN
)
≥ 100 x (gate charge of FET at 10V)
Set Feedback Voltage so that V
)
rises to somewhere between 7.8 and 9.4V, so that
Reference
connecting transformer
0.1µF
DD
rises. This path shuts off altogether
Error Amp Z
+
–
1.0V swept 100Hz – 2.2MHz
●
COMP
V
1
1235 Bordeaux Drive, Sunnyvale, CA 94089
OUT
= V
secondary)
Tektronix
P6021
(1 turn
DIVIDE
± 1.0mV before
DD
= 0, with
V
2
60.4K
40.2K
DD
for
5
Bias Circuit
An external bias resistor, connected between the BIAS pin
and VSS is required by the HV9112 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. The nominal external bias current requirement is 15 to
20µA, which can be set by a 390KΩ to 510KΩ resistor if a
10V V
12V. A precision resistor is not required; ± 5% is fine.
Clock Oscillator
The clock oscillator of the HV9112 consists of a ring of
CMOS inverters, timing capacitors, and, a frequency divid-
ing flip-flop. A single external resistor between the OSC IN
and OSC OUT is required to set the oscillator frequency (see
graph). One major difference exists between the Supertex
HV9112 and competitive 9112s. On the Supertex part, the
oscillator is shut off when a shutoff command is received.
This saves about 150µA of quiescent current, which aids in
the construction of power supplies that meet CCITT specifi-
cation I-430, and in other situations where an absolute mini-
mum of quiescent power dissipation is required.
0.1V swept 10Hz – 1MHz
DD
is used, or a 510kΩ to 680KΩ resistor if V
10.0V
●
Tel: [phone]
4.00V
Reference
100K1%
0.1µF
PSRR
●
www.supertex.com
+
–
100K1%
V
2
V
HV9112
1
DD
will be