CRD-5381 Cirrus Logic Inc, CRD-5381 Datasheet - Page 10

• Manufacturer Part Number: CRD-5381
• Description: Audio Modules & Development Tools Ref Bd high perfm ADC & SRC
• Manufacturer: Cirrus Logic Inc

Specifications of CRD-5381

• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5381, CS8421
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
2.4
2.5
.
System Status Indicators
ADC Overflow - Overflow indicators are provided for each CS5381. Overflow is indicated by the LED la-
beled ADC OVERFLOW A (D4) or ADC OVERFLOW B (D5) being lit. These control signals are also avail-
able as outputs on header J16, labeled OVERFLOW A and OVERFLOW B as shown in
11.
SRC Unlock - SRC unlock indicators are provided for each CS8421. SRC unlock is indicated by the LED
labeled SRC UNLOCK A (D3) or SRC UNLOCK B (D2) being lit. These control signals are also available
as outputs on header J16, labeled SRC UNLOCK A and SRC UNLOCK B as shown in
System Reset
The CRD5381 provides an on-board reset and a connection for a user-applied reset signal through header
J16.
On-board Reset - The on-board reset signal is activated either upon power-up or by pressing push-button
S1. The reset signal is active-low, and is held low for approximately 350 ms after S1 has been pressed, or
power has been applied to the CRD5381.
External Reset - A connection is provided for a user to apply an external reset to the CRD5381 through
header J16 as shown in
When an external reset signal is connected to the CRD5381, the on-board reset is the logical OR of the
power-up reset, the push-button reset, and the external reset.
LJ
LJ
LJ
TDM
TDM
TDM
Table 2
clock frequencies.
J8
indicates the jumper options for J8 with the associated output data formats and some common
SDOUTA Data Format
24-bit Left-Justified
24-bit Left-Justified
24-bit Left-Justified
Figure 6. Clock and Data Header Connections, J4
Figure 7 on page
Table 2. Clock and Data Formatting Options
-
-
-
TDM/SDOUT B
LRCK INPUT
SCLK INPUT
SDOUT A
11. The external reset should be an active-low, +3.3 V signal.
TDM/SDOUTB Data
24-bit Left-Justified
24-bit Left-Justified
24-bit Left-Justified
4-Channel TDM
4-Channel TDM
4-Channel TDM
Signal
Format
J4
Ground
LRCK INPUT
Frequency
192 kHz
192 kHz
48 kHz
96 kHz
48 kHz
96 kHz
SCLK INPUT
12.288 MHz
12.288 MHz
24.576 MHz
Frequency
3.072 MHz
6.144 MHz
6.144 MHz
Figure 7 on page
Figure 7 on page
CRD5381
DS563RD1
11.