CRD-5381 Cirrus Logic Inc, CRD-5381 Datasheet
CRD-5381
Specifications of CRD-5381
Related parts for CRD-5381
CRD-5381 Summary of contents
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... TDM IN CS5381 B CS8421 B Quad Speed Master Input SDOUT SDIN Slave Mode Slave Output Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) CRD5381 SDOUT TDM ENABLE SDOUT A PCM Data Ouput/ Serial Clock Input Header, J4 TDM/SDOUT B LRCK INPUT SDOUT DS563RD1 SCLK INPUT ...
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... CS8421 adds the functionality to output properly dithered 32, 20, or 16-bit data. The CRD5381 was designed as a platform for easy evaluation of the jitter rejection, sample rate conversion, and time-division multiplexing capabilities of the CS8421 in the context of a A/D conversion system with an asynchro- nous decimation filter ...
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... Figure 10. Analog Inputs 3 & 4...................................................................................................... 14 Figure 11. CS5381 & CS8421 Pair A............................................................................................ 15 Figure 12. CS5381 & CS8421 Pair B............................................................................................ 16 Figure 13. I/O Header and Miscellaneous..................................................................................... 17 Figure 14. Power........................................................................................................................... 18 Figure 15. Silk Screen................................................................................................................... 19 Figure 16. Top Layer..................................................................................................................... 20 Figure 17. Bottom Layer................................................................................................................ 21 Figure 18. Power Plane................................................................................................................. 22 Figure 19. Ground Plane............................................................................................................... 23 DS563RD1 CRD5381 3 ...
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... In this application multiple CS8421 inputs are set to master mode, and it is important that their serial ports be aligned in time, with minimum possible phase error. To achieve this, their reset signals are tied together and routed for minimum skew. The amount of deviation between ILRCKs generated by the respective parts is typically either master clock period, or between 0 and 40 ns. 4 CRD5381 . DS563RD1 ...
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... Output word-length and serial data format are selected with either a pull-up or pull down resistor connected to the SAOF pin of the CS8421. Please refer to Table 3 in the CS8421 data sheet for details [3]. The serial audio output of the CRD5381 is configured to operate in either dual 24-bit Left-Justified formats or a 4-channel 24-bit TDM output. ...
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... This phase delay is equal across multiple parts. Therefore, when multiple parts operate at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched. 6 Output Sample Rate Group Delay 48 kHz 1. kHz .895 ms 192 kHz .605 ms Table 1. System Latency CRD5381 Table 1 shows the combined group delay for DS563RD1 ...
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... Filter Response The transition-band response of the CRD5381 is due to the combination of the digital filtering performed by both the CS5381 and the CS8421. Due to the superior stop-band rejection of the CS8421, the combination of the two parts yields a better stop-band rejection then the CS5381 alone. When the output sample rate is close to that of the CS5381, signals that fall within the transition-band spectrum will already have been aliased down into the pass-band prior to the CS8421’ ...
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... B - -45 -50 -55 -60 -65 -70 -75 -80 40k 50k 8 43k 44k 45k 46k 47k Hz Figure 2. Transitional Band, 96 kHz Out 60k 70k 80k 90k 100k Hz Figure 3. Transitional Band, 192 kHz Out CRD5381 48k 49k 50k 51k 52k 110k 120k 130k 140k 150k DS563RD1 ...
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... Audio Data Output Format Selection The CRD5381 allows selection of either a standard Left-Justified 3-wire serial audio interface with sepa- rate data lines for each ADC / SRC pair or a 4-channel TDM interface. Selection of either mode is accom- plished via jumper J8. The two possible serial audio output formats are shown in ...
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... External Reset - A connection is provided for a user to apply an external reset to the CRD5381 through header J16 as shown in Figure 7 on page When an external reset signal is connected to the CRD5381, the on-board reset is the logical OR of the power-up reset, the push-button reset, and the external reset. 10 ...
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... Power The CRD5381 requires the user to supply +3.3 V (J6) and ±12 V (J2 and J1) to the board. Onboard regula- tors supply the required +5 V and +2.5 V. All voltage inputs must be referenced to the single black banana- type ground connector (J5). Zener Diodes Z1 and Z2 (shown in circuitry from accidental connection of a reversed polarity supply or a supply of over ± ...
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BLOCK DIAGRAM Figure 11 on page 15 LEFT RIGHT 2 2 Figure 9 on page 13 & Figure 10 on page 14 Differential Analog Inputs 1 LEFT RIGHT Figure 12 on page 16 Figure 11 on page ...
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SCHEMATICS Figure 9. Analog Inputs 1 & 2 ...
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Figure 10. Analog Inputs 3 & 4 ...
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Figure 11. CS5381 & CS8421 Pair A ...
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Figure 12. CS5381 & CS8421 Pair B ...
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Figure 13. I/O Header and Miscellaneous ...
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Figure 14. Power ...
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... LAYOUT DS563RD1 Figure 15. Silk Screen CRD5381 19 ...
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... Figure 16. Top Layer CRD5381 DS563RD1 ...
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... DS563RD1 Figure 17. Bottom Layer CRD5381 21 ...
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... Figure 18. Power Plane CRD5381 DS563RD1 ...
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... DS563RD1 Figure 19. Ground Plane CRD5381 23 ...
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... AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 24 Changes 1st Release Table 3. Revision History CRD5381 DS563RD1 ...