CDB49300 Cirrus Logic Inc, CDB49300 Datasheet - Page 51

• Manufacturer Part Number: CDB49300
• Description: Audio Modules & Development Tools Eval Bd Mult-Std Aud Decdr. DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CDB49300

• Description/function: Audio A/D
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write
Enable or General Purpose Input & Output Number 10: Pin 4
CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18
RESET—Master Reset Input: Pin 36
SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port
Type Select: Pin 19
EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number
8: Pin 21
INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20
AUDATA2—Digital Audio Output 2: Pin 39
DS262F2
In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In
Motorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial
host mode, this pin can serve as the external-memory active-low write-enable output signal.
Also in serial host mode, this pin can serve as a general purpose input or output bit.
BIDIRECTIONAL - Default: INPUT
In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host
SPI mode, this pin is used as the active-low chip-select input signal. INPUT
Asynchronous active-low master reset input. Reset should be low at power-up to initialize the
CS4923/4/5/6/7/8/9 and to guarantee that the device is not active during initial power-on
stabilization periods. At the rising edge of reset the host interface mode is selected contingent
on the state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated
if a serial control mode is selected and ABOOT is held low. If reset is low all bidirectional pins
are high impedance inputs. INPUT
In I
serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of
RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. In
parallel host mode, after the bus mode has been selected, the pin can function as a general-
purpose input or output pin. BIDIRECTIONAL - Default: INPUT
In I
In serial control port mode, this pin can serve as an output to provide the chip-select for an
external byte-wide ROM. In parallel and serial host mode, this pin can also function as a
general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT
Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has
outgoing control data and should be serviced by the host. Also in serial host mode, this signal
initiates an automatic boot cycle from external memory if it is held low through the rising edge
of reset. OPEN DRAIN I/O - Requires 4.7k Ohm Pull-Up
PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM
output defaults to DGND as output until enabled by the DSP software. OUTPUT
2
2
C mode this pin is an OPEN DRAIN I/O and requires a 4.7k Pull-Up
C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin
CS4923/4/5/6/7/8/9
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