CDB49300 Cirrus Logic Inc, CDB49300 Datasheet - Page 12

• Manufacturer Part Number: CDB49300
• Description: Audio Modules & Development Tools Eval Bd Mult-Std Aud Decdr. DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CDB49300

• Description/function: Audio A/D
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING CHARACTERISTICS—SPI CONTROL PORT
(T
Notes: 5. The specification f
12
SCCLK clock frequency
CS falling to SCCLK rising
Rise time of SCCLK line
Fall time of SCCLK lines
SCCLK low time
SCCLK high time
Setup time SCDIN to SCCLK rising
Hold time SCCLK rising to SCDIN
Transition time from SCCLK to SCDOUT valid
Time from SCCLK rising to INTREQ rising
Rise time for INTREQ
Hold time for INTREQ from SCCLK rising
Time from SCCLK falling to CS rising
High time between active CS
Time from CS rising to SCDOUT high-Z
A
= 25 C; VA, VD = 3.3 V 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull
11. This time is by design and not tested.
6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.
7. SCDOUT should not be sampled during this time period.
8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
second-to-last bit of the last byte of data during a read operation as shown.
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Raise chip select to end the current read transaction and then
drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.
up value will affect the rise time.
sck
Parameter
indicates the maximum speed of the hardware. The system designer should be
(Note 9, 11)
(Note 11)
(Note 11)
(Note 11)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
(Note 8)
Symbol
L
t
t
t
t
= 20 pF)
t
scdov
t
sccsh
t
cscdo
t
cdisu
t
f
t
t
cdih
scrh
csht
sck
css
sch
scrl
t
scl
t
t
rr
r
f
CS4923/4/5/6/7/8/9
Min
150
150
200
20
50
50
20
0
-
-
-
-
-
-
(Note
2000
Max
200
10)
50
50
40
10
-
-
-
-
-
-
-
-
DS262F2
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns