CDB49300 Cirrus Logic Inc, CDB49300 Datasheet - Page 35

• Manufacturer Part Number: CDB49300
• Description: Audio Modules & Development Tools Eval Bd Mult-Std Aud Decdr. DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CDB49300

• Description/function: Audio A/D
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS49300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS262F2
Host Message (HOSTMSG) Register, A[1:0] = 00b
HOSTMSG7–0
Host Control (CONTROL) Register, A[1:0] = 01b
Reserved
CMPRST
PCMRST
MFC
MFB
HINBSY
HOUTRDY
Reserved
PCM Data Input (PCMDATA) Register, A[1:0] = 10b
PCMDATA7–0
Compressed Data Input (CMPDATA) Register, A[1:0] = 11b
CMPDATA7–0
HOSTMSG7
PCMDATA7
CMPDATA7
Reserved
7
7
7
7
HOSTMSG6
PCMDATA6
CMPDATA6
CMPRST
the internal DSP and the external host. This register typically passes multibyte messages car-
rying microcode, control, and configuration data. HOSTMSG is physically implemented as two
independent registers for input and output. (Read and write)
holds the port in reset. Writing zero enables the port. This bit must be low for normal operation.
(Write only)
of the left channel for a PCM stream. Writing a one to this bit holds the port in reset. Writing zero
enables the port. This bit must be low for normal operation. (Write only)
level is application code dependent. (Read only)
level is application code dependent. (Read only)
register. The host reads this bit to determine if the last host byte written has been read by the
DSP. (Read only)
the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has
been read by the host. (Read only)
Host data to and from the DSP. A read or write of this register operates handshake bits between
Always write a 0 for future compatibility.
When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit
When set, initializes the linear PCM input channel. This bit is toggled to indicate the first sample
When high, indicates that the PCMDATA input buffer is almost full. The input buffer threshold
When high, indicates that the CMPDATA input buffer is almost full. The input buffer threshold
Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG
Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from
Always write a 0 for future compatibility.
The host writes PCM data to the DSP input buffer at this address. (Write only)
The host writes compressed data to the DSP input buffer at this address. (Write only)
6
6
6
6
HOSTMSG5
PCMDATA5
CMPDATA5
PCMRST
5
5
5
5
Table 5. Parallel Input/Output Registers
HOSTMSG4
PCMDATA4
CMPDATA4
MFC
4
4
4
4
HOSTMSG3
PCMDATA3
CMPDATA3
MFB
3
3
3
3
HOSTMSG2
PCMDATA2
CMPDATA2
HINBSY
2
2
2
2
CS4923/4/5/6/7/8/9
HOSTMSG1
PCMDATA1
CMPDATA1
HOUTRDY
1
1
1
1
HOSTMSG0
PCMDATA0
CMPDATA0
Reserved
0
0
0
0
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