S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 173

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. BLOCK DESCRIPTION
System Bus
Data transfer
The S1D15400 driver uses the A0, E (or RD) and R/W (or
WR) signals to transfer data between the system MPU
and internal registers. The combinations used are given
in the table below.
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers,
all data is latched into and out of the driver. This
introduces a one cycle delay between a read request for
data and the data arriving. For example, when the MPU
executes a read cycle to access display RAM, the current
contents of the latch are placed on the system data bus
while the desired contents of the display RAM are moved
into the latch.
By using an MPU data bus I/O latch the display data
S1D15400 Series
6–8
Common
A0
1
1
0
0
68 MPU
R/W
1
0
1
0
RD
0
1
0
1
80 MPU
WR
EPSON
1
0
1
0
RAM access timing is determined by the driver cycle
time, t
strategy leads to faster data transfers between the driver
and the MPU.
If the MPU access frequency is likely to exceed 1/t
then the designer has the choice of inserting NOPs into
the access loop or polling the driver, by reading the busy
flag, to see if it will accept new data or instructions.
This means that a dummy read cycle has to be executed
at the start of every series of reads.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
Read display data
Write display data
Read status
Write to internal register (command)
cyc
, not by the RAM access time. In general this
Function
Rev. 1.0
cyc
,