P5DF081X0T1AD2060S NXP Semiconductors, P5DF081X0T1AD2060S Datasheet - Page 5

• Manufacturer Part Number: P5DF081X0T1AD2060S
• Description: IC SAM MIFARE 8PLLCC
• Manufacturer: NXP Semiconductors

Specifications of P5DF081X0T1AD2060S

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
P5DF081_SDS
Objective short data sheet
PUBLIC
8.2.1.1 Answer To Reset (ATR)
8.1.3 Card operation procedures
8.2.1 Protocol activation sequence
8.2 Transmission procedure and communication
The maximum specified bit rate in any case is 1.5 Mbit/s.
All card operation procedures (activation, cold reset, warm reset and deactivation) are
fully compliant with
All subsequently described operations are compliant with ISO/IEC 7816-3.
The MIFARE SAM AV2 offers two modes of operation identified by different ATRs.
A negotiable mode where the bit rate has to be adjusted via a PPS request and a specific
mode where the MIFARE SAM AV2 switches automatically to F = 128 and D = 32 (highest
possible speed) after sending the ATR. Starting with the negotiable mode, the mode of
operation is switched after every warm reset.
After a cold reset, the card sends the following ATR to the terminal.
Table 4.
After this ATR, the card is in the negotiable mode and waits for a PPS request. If a warm
reset is issued, the MIFARE SAM AV2 switches the mode of operation, enters the specific
mode and sends the following ATR.
Character
TS
T0
TA(1)
TC(1)
TD(1)
TD(2)
TA(3)
TB(3)
TC(3)
TD(3)
TA(after T = 15)
TB(after T = 15)
Historical bytes
TCK
ATR after cold reset
All information provided in this document is subject to legal disclaimers.
Value
3Bh
DFh
18h
FFh
81h
F1h
FEh
43h
00h
3Fh
03h
83h
4Dh, 49h, 46h, 41h, 52h,
45h, 20h, 50h, 6Ch, 75h,
73h, 20h, 53h, 41h, 4Dh
3B
Ref.
Rev. 1 — 12 August 2010
19, Chapter 5.
191710
Meaning
initial character; setting up direct convention
TA(1), TC(1), TD(1) are present; number of
historical characters is 15
F = 372; D = 12
no extra guard time needed; N = 255
TD(2) is present; protocol T = 1
TA(3), TB(3), TC(3) and TD(3) are present; protocol
T = 1
Information field size of the card = 254
BWT indicator = 4; CWT indicator = 3
error detection code = LRC
TA and TB for T = 15 is present; protocol T = 15
(qualifies global interface bytes)
clock stop not supported; Class A, Class B
Proprietary use of C6 (IO3, reception of serial data
from RC222)
ASCII value of “MIFARE Plus SAM”
check character
P5DF081
MIFARE SAM AV2
© NXP B.V. 2010. All rights reserved.
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