IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 244
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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15–16
Table 15–8. Fields in the DMA Write Status High Register
Table 15–9. Fields in the DMA Read Status High Register
PCI Express Compiler User Guide
[23:21]
[20:17]
16
[15:0]
[31:25]
24
[23:21]
[20:17]
16
[15:0]
Bit
Bit
Max payload size
Reserved
Write DMA descriptor FIFO empty
Write DMA EPLAST
Board number
Reserved
Max Read Request Size
Negotiated Link Width
Read DMA Descriptor FIFO Empty
Read DMA EPLAST
Table 15–9
are read only.
Field
Field
describes the fields in the DMA read status high register. All of these fields
Indicates to the software application which board is being used. The
following encodings are defined:
■
■
■
■
■
■
■
■
The following encodings are defined:
■
■
■
■
■
The following encodings are defined:
■
■
■
■
Indicates that there are no more descriptors pending in the read DMA.
Indicates the number of the last descriptor completed by the read DMA.
The following encodings are defined:
■
■
■
■
■
Indicates that there are no more descriptors pending in the write DMA.
Indicates the number of the last descriptor completed by the write DMA.
0 Altera Stratix II GX ×1
1 Altera Stratix II GX ×4
2 Altera Stratix II GX ×8
3 Cyclone II ×1
4 Arria GX ×1
5 Arria GX ×4
6 Custom PHY ×1
7 Custom PHY ×4
001 128 bytes
001 256 bytes
010 512 bytes
011 1024 bytes
100 2048 bytes
0001 ×1
0010 ×2
0100 ×4
1000 ×8
001 128 bytes
001 256 bytes
010 512 bytes
011 1024 bytes
100 2048 bytes
Description
Description
—
—
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
Chaining DMA Design Example
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