IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 223

• Manufacturer Part Number: IPR-PCI/MT64
• Description: IP CORE Renewal Of IP-PCI/MT64
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT64

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 64 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
any address that is within the BAR1 range results in an io_hit action.
Refer to the target transactor source code to see how the address is
decoded for io_hit.
1
The target transactor idsel signal should be connected to one of the PCI
address bits in the top-level file of the PCI testbench for configuration
transactions to occur on BAR0 and BAR1.
To model different target terminations, use the following three input
signals:
■
■
■
The target transactor has two main sections:
■
■
FILE IO section
Upon reset, this section initializes the target transactor memory array
with the contents of the trgt_tranx_mem_init.dat file, which must be in
the project's working directory. Each line in the trgt_tranx_mem_init.dat
file corresponds to a memory location, the first line corresponding to
offset "000". The number of lines defined by the address_lines
parameter in the target transactor source code should be equal to number
of lines in the trgt_tranx_mem_init.dat file. If the number of lines in
trgt_tranx_mem_init.dat file is less than the number of lines defined by
the address_lines parameter, the remaining lines in the memory array
are initialized to 0.
PROCEDURES and TASKS sections
The PROCEDURES section (VHDL) and the corresponding TASKS
section (Verilog HDL) define the events to be executed for the decoded
PCI transaction. These sections are fully documented in the source code.
You can modify the procedures or tasks to introduce different variations
trgt_tranx_retry—The target transactor retries the memory
transaction if trgt_tranx_retry is set to one
trgt_tranx_discA—The target transactor terminates the memory
transaction with data if trgt_tranx_discA is set to one
trgt_tranx_discB—The target transactor terminates the memory
transaction with a disconnect without data if trgt_tranx_discB
is set to one
FILE IO
PROCEDURES (VHDL) and TASKS (Verilog HDL)
The target transactor ignores byte enables for all memory, I/O,
and configuration transactions.
PCI Compiler Version 10.1
PCI Compiler User Guide
Testbench
4–13