IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 111
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Figure A–1. Start-Up Sequence Flowchart
December 2010 Altera Corporation
Configure TX function
enable status FSM
TX system clocks
stabilize
(2a)
and
(4)
This appendix applies to any SPI-4.2 transmitter and receiver pair, where at least one
is an Altera
The startup sequence combines clock stabilization, reset, and configuration with the
training and framing aspects of the SPI-4.2 protocol as shown in
page
function are listed in
implementations.
Release TX core reset
TX frames on status
disable status FSM
TX ready
A–1. Details of each event as they happen in the POS-PHY Level 4 MegaCore
(6)
and
(3)
®
POS-PHY Level 4 MegaCore
TX sends training
TX PL4 clocks
stabilize
(2b)
(3)
Table
RX sends 'b11 status
Assert all resets
A–1, but similar events should happen in other SPI-4.2
Power up
(1)
stabilized and trained
RX PL4 clocks
RX DPA
®
stabilize
(5a)
(2b)
function.
Release RX core reset
Sends status frames
disable status FSM
POS-PHY Level 4 MegaCore Function User Guide
A. Start-Up Sequence
RX ready
(6)
and
(3)
Configure RX function
RX system clocks
enable status FSM
stabilize
Figure A–1 on
(2a)
and
(4)
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