EVAL-ADUC812QSZ Analog Devices Inc, EVAL-ADUC812QSZ Datasheet - Page 39

• Manufacturer Part Number: EVAL-ADUC812QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC812
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC812
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

IE2
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt.
An interrupt of high priority may interrupt the service routine of
a low priority interrupt. If two interrupts of different priorities
occur at the same time, the higher level interrupt will be served
first. An interrupt cannot be interrupted by another interrupt of
the same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed, as shown
in Table XXV.
Source
PSMI
IE0
ADCI
TF0
IE1
TF1
I2CI + ISPI
RI + TI
TF2 + EXF2
REV. E
—
Table XXV. Priority within an Interrupt Level
Name
—
—
—
—
—
—
EPSMI
ESI
Priority
1 (Highest)
2
3
4
5
6
7
8
9 (Lowest)
—
Description
Power Supply Monitor Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
I
Serial Interrupt
Timer/Counter 2 Interrupt
2
C/SPI Interrupt
Secondary Interrupt
Enable Register
A9H
00H
No
Description
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Written by user to Enable “1” or Disable “0” power supply monitor interrupt.
Written by user to Enable “1” or Disable “0” I
—
Table XXIV. IE2 SFR Bit Designations
—
–39–
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in the Table XXVI.
—
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ADCI
I2CI + ISPI
PSMI
Table XXVI. Interrupt Vector Addresses
2
C/SPI serial port interrupt.
—
E
P
S
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
M
I
ADuC812
E
S
I