EVAL-AD7747EBZ Analog Devices Inc, EVAL-AD7747EBZ Datasheet
EVAL-AD7747EBZ
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EVAL-AD7747EBZ Summary of contents
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FEATURES Capacitance-to-digital converter New standard in single chip solutions Interfaces to single or differential grounded sensors Resolution down (that is 19.5-bit ENOB) Accuracy Linearity: 0.01% Common-mode (not changing) capacitance ...
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AD7747 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. ...
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SPECIFICATIONS 5.25 V; GND = 0 V; EXC = ±V DD Table 1. Parameter CAPACITIVE INPUT Conversion Input Range 2 Integral Nonlinearity (INL) No Missing Codes 2 Resolution, p-p ...
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AD7747 Parameter 5 Normal Mode Rejection 2 Common-Mode Rejection INTERNAL VOLTAGE REFERENCE Voltage Drift vs. Temperature EXTERNAL VOLTAGE REFERENCE INPUT 2 Differential REFIN Voltage 2 Absolute REFIN Voltage Average REFIN Input Current Average REFIN Input Current Drift Common-Mode Rejection SERIAL ...
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TIMING SPECIFICATIONS 5.25 V; GND = 0 V; Input Logic Input Logic Table 2. Parameter 1, 2 SERIAL INTERFACE SCL Frequency ...
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AD7747 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Positive Supply Voltage V to GND DD Voltage on any Input or Output Pin to GND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCL Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system. 2 RDY Logic Output. ...
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AD7747 TYPICAL PERFORMANCE CHARACTERISTICS –20 –40 –60 –80 –8 –7 –6 –5 –4 –3 –2 – INPUT CAPACITANCE (pF) Figure 4. Capacitance Input Integral Nonlinearity CAPDAC = 0x3F DD ...
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PARALLEL RESISTANCE (MΩ) Figure 10. Capacitance Input Error vs. Parallel Resistance; CIN(+) to GND = 8 pF –100 –200 –300 –400 –500 –600 –700 –800 –900 –1000 0 ...
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AD7747 200 150 100 50 0 –50 –100 –150 –200 CAPDAC CODE Figure 16. CAPDAC Differential Nonlinearity (DNL) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 – TEMPERATURE (°C) Figure ...
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... CIN and SHLD DD pins connected only to the evaluation board (no external capacitors). Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time (Bold line represents default setting) Conversion Output Data − ...
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AD7747 SERIAL INTERFACE 2 The AD7747 supports an I C-compatible 2-wire serial interface. 2 The two wires on the I C bus are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one ...
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Therefore, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. AD7747 RESET To reset the AD7747 without having to ...
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AD7747 REGISTER DESCRIPTIONS The master can write to or read from all of the AD7747 registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. ...
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STATUS REGISTER Address Pointer 0x00, Read Only, Default Value 0x07 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. The RDY pin reflects the status ...
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AD7747 CAP SETUP REGISTER Address Pointer 0x07, Default Value 0x00 Capacitive channel setup. Table 11. Cap Setup Register Bit Map Bit Bit 7 Mnemonic CAPEN Default 0 Table 12. Bit Mnemonic Description 7 CAPEN CAPEN = 1 enables capacitive channel ...
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EXC SETUP REGISTER Address Pointer 0x09, Default Value 0x03 Capacitive channel excitation setup. Table 15. EXC Setup Bit Map Bit Bit 7 Mnemonic – Default 0 Table 16. Bit Mnemonic Description – These bits must be 0 ...
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AD7747 CONFIGURATION REGISTER Address Pointer 0x0A, Default Value 0xA0 Converter update rate and mode of operation setup. Table 17. Configuration Register Bit Map Bit Bit 7 Mnemonic VTFS1 Default 0 Table 18. Bit Mnemonic Description 7 VTFS1 Voltage/temperature channel digital ...
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CAP DAC A REGISTER Address Pointer 0x0B, Default Value 0x00 Capacitive DAC setup. Table 19. Cap DAC A Register Bit Map Bit Bit 7 Mnemonic DACAENA Default 0 Table 20. Bit Mnemonic Description 7 DACAENA DACAENA = 1 connects capacitive ...
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AD7747 CAP OFFSET CALIBRATION REGISTER 16 Bits, Address Pointer 0x0D, 0x0E, Default Value 0x8000 The capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. The coefficient is used to digitally remove the capacitive channel offset. The register value ...
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CIRCUIT DESCRIPTION TEMP SENSOR CLOCK GENERATOR VIN(+) VIN(–) 24-BIT Σ-Δ MUX GENERATOR CIN1(+) CIN1(–) SHLD CAP DAC 1 EXCITATION CAP DAC 2 REFIN(+) REFIN(–) Figure 24. AD7747 Block Diagram OVERVIEW The AD7747 core is a high precision converter consisting of ...
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AD7747 The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. There are two independent CAPDACs, one connected to the CIN(+) and the second con- nected to the CIN(−). The relation between the capacitance input ...
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CAPDAC(+) 17pF CIN(+) CAPDIFF = 1 CIN(–) CAPDAC(–) 17pF 25pF 17pF (17pF ± 8pF) SHLD Figure 32. Using CAPDAC in Differential Configuration PARASITIC CAPACITANCE The CDC architecture used in the AD7747 measures the capacitance ...
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AD7747 CAPACITIVE SYSTEM OFFSET CALIBRATION The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any parasitic capacitance of tracks on the board, and the capacitance of any other connections ...
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VOLTAGE INPUT VDD ANALOG TO DIGITAL CONVERTER (ADC) CLOCK GENERATOR VIN(+) 24-BIT Σ-Δ R RTD T MODULATOR VIN(–) REFIN(+) R REF REFIN(–) Figure 38. Resistive Temperature Sensor Connected to the Voltage Input The AD7747 Σ-Δ core can work as a ...
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AD7747 TYPICAL APPLICATION DIAGRAM TEMP SENSOR VIN (+) VIN (–) CIN1(+) CIN1(–) SHLD EXCITATION Figure 39. Basic Application Diagram for a Differential Capacitive Sensor 0.1µF VDD CLOCK AD7747 GENERATOR 24-BIT Σ-Δ DIGITAL MUX GENERATOR FILTER INTERFACE CONTROL LOGIC CALIBRATION VOLTAGE ...
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... OUTLINE DIMENSIONS 0.15 0.05 ORDERING GUIDE Model Temperature Range 1 AD7747ARUZ −40°C to +125°C 1 AD7747ARUZ-REEL −40°C to +125°C AD7747ARUZ-REEL7 1 −40°C to +125°C 1 EVAL-AD7747EBZ Pb-free part. 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0.65 0° ...
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AD7747 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...