AFCT-701SDDZ Avago Technologies US Inc., AFCT-701SDDZ Datasheet - Page 8

• Manufacturer Part Number: AFCT-701SDDZ
• Description: 10G/1G Dual Data Rate SFP+LR,RoHS
• Manufacturer: Avago Technologies US Inc.

Specifications of AFCT-701SDDZ

• Data Rate: 10.312Gbd
• Wavelength: 1310nm
• Applications: Ethernet
• Voltage - Supply: 3.135 V ~ 3.465 V
• Connector Type: LC Duplex
• Mounting Type: SFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2. Contact Description
Contact Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Notes:
1. The module signal grounds are isolated from the module case.
2. This is an open collector/drain output that on the host board requires a 4.7 k: to 10 k: pullup resistor to VccHost. See Figure 2.
3. This input is internally biased high with a 4.7 k: to 10 k: pullup resistor to VccT.
4. Two-Wire Serial interface clock and data lines require an external pullup resistor dependent on the capacitance load.
5. This is a ground return that on the host board requires a 4.7 k: to 10 k: pullup resistor to VccHost.
6. Refer to the Appendix for detailed operation of RS0 and RS1.
Figure 3. Module edge connector contacts
8
TOWARD
HOST
10
1
VeeT
TX_FAULT
TX_DISABLE
SDA
SCL
MOD_ABS
RS0
RX_LOS
RS1
VeeR
VeeR
RD-
RD+
VeeR
VccR
VccT
VeeT
TD+
TD-
VeeT
BOTTOM OF
BOARD AS
VIEWED FROM
TOP THROUGH
BOARD
Function/Description
Transmitter Signal Ground
Transmitter Fault (LVTTL-O) – High indicates a fault condition
Transmitter Disable (LVTTL-I) – High or open disables the transmitter
Two Wire Serial Interface Data Line (LVCMOS – I/O)
(same as MOD-DEF2 in INF-8074)
Two Wire Serial Interface Clock Line (LVCMOS – I/O)
(same as MOD-DEF1 in INF-8074)
Module Absent (Output), connected to VeeT or VeeR in the module
Rate Select 0 - RS0=Lo for 1000BASE-LX, RS0=Hi for 10GBASE-LR
Receiver Loss of Signal (LVTTL-O)
Rate Select 1 - RS1=Lo for 1000BASE-LX, RS1=Hi for 10GBASE-LR
Receiver Signal Ground
Receiver Signal Ground
Receiver Data Out Inverted (CML-O)
Receiver Data Out (CML-O)
Receiver Signal Ground
Receiver Power + 3.3 V
Transmitter Power + 3.3 V
Transmitter Signal Ground
Transmitter Data In (CML-I)
Transmitter Data In Inverted (CML-I)
Transmitter Signal Ground
11
20
TOP VIEW
OF BOARD
Note 2
Note 1
Note 1
Notes
Note 1
Note 2
Note 3
Note 4
Note 4
Note 5
Note 6
Note 6
Note 1
Note 1