AFCT-701SDDZ Avago Technologies US Inc., AFCT-701SDDZ Datasheet - Page 14

• Manufacturer Part Number: AFCT-701SDDZ
• Description: 10G/1G Dual Data Rate SFP+LR,RoHS
• Manufacturer: Avago Technologies US Inc.

Specifications of AFCT-701SDDZ

• Data Rate: 10.312Gbd
• Wavelength: 1310nm
• Applications: Ethernet
• Voltage - Supply: 3.135 V ~ 3.465 V
• Connector Type: LC Duplex
• Mounting Type: SFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Control Functions: Low Speed Signals Timing Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
TX_DISABLE Assert Time
TX_DISABLE Negate Time
Time to initialize, including reset of TX_FAULT
TX_FAULT Assert Time
TX_DISABLE to Reset
RX_LOS Assert Time
RX_LOS Deassert Time
Rate Select Time
Notes:
1. Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal. A 10 ms interval between assertions of
2. Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.
3. Time from power on or falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal and the Two-Wire
4. From power on or negation of TX_FAULT using TX_DISABLE.
5. Time TX_DISABLE must be held high to reset the laser fault shutdown circuitry.
6. Time from loss of optical signal to Rx_LOS Assertion.
7. Time from valid optical signal to Rx_LOS De-Assertion.
Table 10. Control Functions: Two-Wire Interface Timing Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
TX_DISABLE Assert Time
TX_DISABLE Negate Time
TX_FAULT Assert Time
Rx_LOS Assert Time
Rx_LOS Deassert Time
Analog parameter data ready
Two-Wire Interface Ready
Complete Single or Sequential Write up to 4 Byte
Complete Sequential Write of 5-8 Byte
Two-Wire Interface Clock Rate
Time bus free before new
transmission can start
Notes:
1. Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured
2. Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the modulated optical output rises above 90% of
3. Time from fault to two-wire interface TX_FAULT (A2h, byte 110, bit 2) asserted.
4. Time for two-wire interface assertion of Rx_LOS (A2h, byte 110, bit 1) from loss of optical signal.
5. Time for two-wire interface de-assertion of Rx_LOS (A2h, byte 110, bit 1) from presence of valid optical signal.
6. From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is functional.
7. Time from power on until module is ready for data transmission over the two-wire interface (reads or writes over A0h and A2h).
8. Operation of the Two Wire Serial Interface at rtes beyond 100kHz requires the use of clock stretching techniques.
9. Between STOP and START. See SFF 8431 Section 4.3
14
TX_DISABLE is required.
interface is available.
from falling clock edge after stop bit of write transaction.
nominal.
Symbol
t_off
t_on
t_init
t_fault
t_reset
t_los_on
t_los_off
t_rate
Symbol
t_off_twi
t_on_twi
t_fault_twi
t_loss_on_twi
t_loss_off_twi
t_data
t_serial
t_write
t_write
f_serial_clock
t_buf
Minimum
10
Minimum
20
Maximum
100
2
300
1000
100
100
40
Maximum
100
100
100
100
100
1000
300
40
80
400
Unit
Ps
ms
ms
Ps
Ps
Ps
Ps
ms
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
kHz
Ps
Notes
Note 1 , Fig. 5
Note 2 , Fig. 5
Note 3 , Fig. 5
Note 4 , Fig. 5
Note 5 , Fig. 5
Note 6 , Fig. 5
Note 7 , Fig. 5
Notes
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Note 8
Note 8
Note 9