ADNS-2051 Avago Technologies US Inc., ADNS-2051 Datasheet - Page 23

• Manufacturer Part Number: ADNS-2051
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2051

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q2072083C

23
Notes on Power up and the Serial Port
The sequence in which V
during powerup can affect the operation of the serial port.
The diagram below shows what can happen shortly after
powerup when the microprocessor tries to read data from
the serial port.
This diagram shows the V
point the microcontroller starts its program, sets the SCLK
and SDIO lines to be outputs, and sets them high. It then
waits to ensure that the ADNS-2051 has powered up and
is ready to communicate. The microprocessor then tries
to read from location 0x00, Product_ID, and is expecting
a value of 0x02. If it receives this value, it then knows that
the communication to the ADNS-2051 is operational.
The problem occurs if the ADNS-2051 powers up before
the microprocessor sets the SCLK and SDIO lines to be
Figure 36. Power up serial port watchdog timer sequence
Figure 37. Power up serial port PD sync sequence
Two Solutions
There are two different ways to solve the problem, waiting
for the serial port watchdog timer to time out, or using
the PD line to reset the serial port.
1. Serial Port Watchdog Timer Timeout
If the microprocessor waits at least t
valid, it will ensure that the ADNS-2051 has pow-
ered up and the watchdog timer has timed out. This
assumes that the microprocessor and the ADNS-2051
share the same power supply. If not, then the mi-
croprocessor must wait t
valid. Then when the SCLK toggles for the address, the
ADNS-2051 will be in sync with the microprocessor.
V
PD
SCLK
SDIO
V
PD
SCLK
SDIO
DD
DD
4 ms
> t
SPTT
DD
DD
SPTT
, PD, SCLK, and SDIO are set
rising to valid levels, at some
ADDRESS = 0x00
ADDRESS = 0x00
from ADNS-2051 V
SPTT
from V
DD
DD
outputs and high. The ADNS-2051 sees the raising of the
SCLK as a valid rising edge, and clocks in the state of the
SDIO as the first bit of the address (sets either a read or a
write depending upon the state).
In the case of SDIO low, then a read operation has started.
When the microprocessor begins to actually send the
address, the ADNS-2051 already has the first bit of an
address. When the seventh bit is sent by the micro, the
ADNS-2051 has a valid address, and drives the SDIO line
high within 120 ns (see detail “A” in Figure 27 and Figure
28). This results in a bus fight for SDIO. Since the address
is wrong, the data sent back will be incorrect.
In the case of SDIO high, a write operation is started. The
address and data are out of synchronization, and the wrong
data will be written to the wrong address.
2. PD Sync
The PD line can be used to resync the serial port. If the
microprocessor waits for 4 ms from V
outputs a valid PD pulse (see Figure 15), then the serial
port will be ready for data.
Resync Note
If the microprocessor and the ADNS-2051 get out of sync,
then the data either written or read from the registers will
be incorrect. An easy way to solve this is to output a PD
pulse to resync the parts after an incorrect read.
DATA = 0x02
DATA = 0x02
DD
valid, and then