ADNS-2051 Avago Technologies US Inc., ADNS-2051 Datasheet - Page 19

• Manufacturer Part Number: ADNS-2051
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2051

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q2072083C

SCLK
CYCLE #
SCLK
SDIO
DETAIL "A"
MICROCONTROLLER
TO ADNS-2051
SDIO HANDOFF
19
Read Operation
A read operation, which means that data is going from the
ADNS-2051 to the micro-controller, is always initiated by
the micro-controller and consists of two bytes. The first
byte contains the address, is written by the micro-con-
troller, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-2051. The transfer is synchronized by SCLK. SDIO is
changed on falling edges of SCLK and read on every rising
Figure 27. Read operation
Figure 28. Microcontroller to ADNS-2051 SDIO handoff
DETAIL "B"
ADNS-2051 TO
MICROCONTROLLER
SDIO HANDOFF
Figure 29. ADNS-2051 to microcontroller SDIO handoff
1
0
A 6
2
SCLK
SDIO
SDIO DRIVEN BY MICRO-CONTROLLER
SCLK
SDIO
3
A 5
RELEASED BY 2051
A 1
A 4
4
5
A 3
D 0
60 ns, MIN.
6
A 2
120 ns, MIN.
R/W BIT OF NEXT ADDRESS
10 ns, MAX.
DRIVEN BY MICRO
A 1
7
120 ns, MIN.
A 0
A 0
100 μs, MIN.
DETAIL "A"
8
t HOLD
edge of SCLK. The micro-controller must go to a high Z
state after the last address data bit. The ADNS-2051 will
go to the high Z state after the last data bit (see detail “B”
in Figure 28). One other thing to note during a read
operation is that SCLK will need to be delayed after
the last address data bit to ensure that the ADNS-2051
has at least 100 μs to prepare the requested data. This is
shown in the timing diagrams below.
9
D 7
0 ns, MIN.
10
D 6
Note:
The 120 ns high state of SCLK is the minimum
data hold time of the ADNS-2051. Since the
falling edge of SCLK is actually the start of
the next read or write command, the ADNS-
2051 will hold the state of D
until the falling edge of SCLK. In both write
and read operations, SCLK is driven by the
micro-controller.
Serial port communications is not allowed
while PD (power down) is high. See
“Error Detection and Recovery” regarding re-
synchronizing via PD.
11
Hi-Z
D 5
SDIO DRIVEN BY ADNS-2051
12
D 4
120 ns, MAX.
D 7
0 ns, MIN.
13
D 3
14
D 6
D 2
120 ns, MAX.
0
on the SDIO line
15
D 1
16
D 0
DETAIL "B"