ST8024LCDR STMicroelectronics, ST8024LCDR Datasheet - Page 21

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ST8024LCDR

Manufacturer Part Number
ST8024LCDR
Description
IC INTERFACE SMART CARD 28SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST8024LCDR

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STM32 Cortex-M3 Companion Products
Applications
Smart Card Reader, Writer
Voltage - Supply
2.7 V ~ 6.5 V
Package / Case
28-SOIC (0.300", 7.50mm Width)
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-

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ST8024L
5.7
5.8
Figure 7.
Active mode
When the activation sequence is completed, the ST8024L will be in its active mode. Data
are exchanged between the card and the microcontroller via the I/O lines.
The ST8024L is designed for cards without V
the internal non-volatile memory).
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see
1.
2.
3.
4.
5.
6.
7.
Deactivation sequence
RST goes low (t
CLK is held low (t
oscillator (approximately 25 µs).
I/O, AUX1 and AUX2 are pulled low (t
V
The deactivation sequence is complete at t
All card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC
remain at V
The internal oscillator returns to its lower frequency.
CC
starts to fall towards zero (t
DD
(pulled-up via a 11 kΩ resistor).
10
12
).
= t
10
+ 0.5 x T) where T is 64 times the period of the internal
Doc ID 17709 Rev 3
Figure
14
= t
7):
10
13
+ 1.5 x T).
= t
PP
10
de
(the voltage required to program or erase
, when V
+ T).
CC
reaches its inactive state.
Functional description
CS17760
21/33

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