ST8024LCDR STMicroelectronics, ST8024LCDR Datasheet - Page 17

• Manufacturer Part Number: ST8024LCDR
• Description: IC INTERFACE SMART CARD 28SOIC
• Manufacturer: STMicroelectronics

Specifications of ST8024LCDR

• Featured Product: STM32 Cortex-M3 Companion Products
• Applications: Smart Card Reader, Writer
• Voltage - Supply: 2.7 V ~ 6.5 V
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

ST8024L
5.2.2
Note:
5.2.3
5.3
With an external divider on pin PORADJ
In this case, a resistor bridge is applied to the PORADJ pin (see
V
on V
off. By knowing these values and using the formula:
it is possible to set R
device on and off (R
In particular, R
microcontroller off, the smartcard has to be switched off properly as well. The same is true
for the microcontroller startup in that the smartcard has to be turned on after the
microcontroller. The reset pulse width t
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed
when the voltage on pin PORADJ exceeds 1 V.
This ensures that after detection of the external bridge by the IC during power-on, the input
current on pin PORADJ does not cause inaccuracy of the bridge voltage.
The V
for example, the microcontroller is shut down at 2.5 V, appropriate external resistor values
must be chosen to ensure proper deactivation of the ST8024L device.
Application examples
The voltage supervisor is used as power-on reset and as supply dropout detection during a
card session. Supply dropout detection is to ensure that a proper deactivation sequence is
followed before the voltage is too low. For the internal voltage supervisor to function, the
system microcontroller should operate down to 2.35 V to ensure a proper deactivation
sequence. If this is not possible, external resistor values can be chosen to overcome the
problem.
Clock circuitry (only on SO-28 and TSSOP-28 packages)
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f
is made via inputs CLKDIV1 and CLKDIV2 (see
Table 21.
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
TH(ext) fall
between changes is needed. The minimum duration of any state of CLK is eight periods of XTAL1.
DD
th
, respectively. They are the voltages on pin PORADJ that switch the device on and
threshold of the ST8024L is slightly lower (80 mV typ.) than the ST8024 device. If
are the external rising threshold voltage and the external falling threshold voltage
CLKDIV1
Clock frequency selection
0
0
1
1
1
and R
1
1
+ R
and R
2
have to be set so that, when V
2
= 100 kΩ typ).
2
XTAL
in order to get suitable values for V
Doc ID 17709 Rev 3
V
PORADJ
, 1/2 x f
W
= (R
XTAL
is doubled to approximately 16 ms.
CLKDIV2
(1)
2
, 1/4 x f
0
1
1
0
/R
1
Table
+ R
XTAL
2
) x V
DD
21).
or 1/8 x f
is getting low, before turning the
DD
Figure
DD
XTAL
Functional description
in order to turn the
. Frequency selection
1). V
f
f
f
XTAL
XTAL
XTAL
f
f
XTAL
CLK
TH(ext) rise
/8
/4
/2
17/33
and