ADIS16354AMLZ Analog Devices Inc, ADIS16354AMLZ Datasheet - Page 18

• Manufacturer Part Number: ADIS16354AMLZ
• Description: MODULE GYRO/ACCELEROMETER 24LD
• Manufacturer: Analog Devices Inc
• Series: iSensor™r

Specifications of ADIS16354AMLZ

• Output Type: Digital - SPI
• Sensor Type: Gyroscope and Accelerometer
• No. Of Axes: 3
• Sensor Case Style: ML-24-2
• No. Of Pins: 24
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Acceleration Range: ± 1.7g
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With: ADIS16354/PCBZ - BOARD EVAL FOR ADIS16354
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

ADIS16354
Table 15. COMMAND Register Definition
Address
0x3F, 0x3E
Table 16. COMMAND Bit Descriptions
Bits
[15:8]
[7]
[6:5]
[4]
[3]
[2]
[1]
[0]
OPERATIONAL CONTROL
Internal Sample Rate
The internal sample rate defines how often data output variables
are updated, independent of the rate at which they are read out
on the SPI port. The SMPL_PRD register controls the ADIS16354
internal sample rate and has two parts: a time base and a multi-
plier. The sample period can be calculated using the following
equation:
where:
T
T
N
The default value is the minimum register setting, 0x01, which
corresponds to the maximum sample rate of 819.2 samples per
second. The contents of this register are nonvolatile.
Table 17. SMPL_PRD Register Definition
Address
0x37, 0x36
Table 18. SMPL_PRD Bit Descriptions
Bits
[15:8]
[7]
[6:0]
An example calculation of the sample period for the device is
The sample rate setting has a direct impact on the SPI data rate
capability. For SMPL_PRD settings ≤ 0x09 (fast mode), the SPI
SCLK can run at a rate up to 2.0 MHz. For SMPL_PRD settings
S
B
S
is the sample period.
is the time base.
is the multiplier.
T
If SMPL_PRD = 0x0007, Bits [7:0] = 00000111
Bit 7 = 0, so T
Bits [6:0] = 0000111 = 7 = N
T
f
S
S
S
= 1∕T
= T
= T
Description
Not used
Software reset command
Not used
Precision autonull command
Flash update command
Auxiliary DAC data latch
Factory calibration restore command
Autonull command
Description
Not used
Time base, 0 = 0.61035 ms, 1 = 18.921 ms
Multiplier (add 1 before multiplying by the time base)
B
B
S
× (N
× (N
= 204.8 SPS
Default
N/A
Default
0x0001
S
S
+ 1)
+ 1) = 0.61035 ms × (7 + 1) = 4.8828 ms
B
= 0.61035 ms
S
Format
N/A
Format
N/A
Access
Write only
Access
R/W
Rev. A | Page 18 of 18
> 0x09 (normal mode), the SPI SCLK can run at a rate up to
300 kHz.
The sample rate setting also affects the power dissipation.
The normal mode power dissipation is approximately 67% less
than the fast mode power dissipation. The two different modes
of operation offer a system-level trade-off between performance
(sample rate, serial transfer rate) and power dissipation.
Power Management
The ADIS16354 offers two different shutdown options:
programmable shutdown period and indefinite shutdown.
Raising Bit 8 activates the indefinite shutdown period. Writing
the appropriate sleep time to the lower byte of the SLP_CNT
register shuts the device down for the specified time. The
following example illustrates this relationship:
At the completion of the programmed duration, the ADIS16354
returns to normal operation. If measurements are required
before sleep period completion or if it is necessary to end the
indefinite shutdown, the ADIS16354 can be awakened by pull-
ing the CS line down to a 0 state, then returning it to a 1 state.
Otherwise, the CS line must be kept in a 1 state to maintain sleep
mode.
When writing a sleep time to the SLP_CNT register, the CS
signal must be raised to a 1 before the command takes effect.
Power cycle recovery will be a normal startup, because the
contents of SLP_CNT are volatile.
Table 19. SLP_CNT Register Definition
Address
0x3B, 0x3A
1
Table 20. SLP_CNT Bit Descriptions
Bits
[15:9]
[8]
[7:0]
Digital Filtering
Each sensor’s signal conditioning circuit has an analog bandwidth
of approximately 350 Hz. The ADIS16354 provides a Bartlett
Window FIR filter for additional noise reduction on all of the
output data registers. The SENS/AVG register controls the
number of taps in power-of-two step sizes, from zero to six
Filter setup requires one simple step: write the appropriate M
factor to the assigned bits in the SENS/AVG register. The bit
assignments are listed in Table 22. The frequency response
relationship for this filter is:
Scale is the weight of each LSB in the lower byte of this register.
Bits [7:0] = 00000110 = 6 codes = 3 seconds
H
B
(
f
Description
Not used
Indefinite shutdown control bit
Data bits, 0.5 sec/LSB
)
=
Scale
0.5 sec
H
A
2
(
f
1
)
H
Default
0x0000
A
(
f
)
=
sin
N
×
Format
Binary
(
π
sin
×
(
N
π
×
×
f
f
×
×
Access
R/W
t
t
s
s
)
)