PIC18LF4682-I/ML Microchip Technology, PIC18LF4682-I/ML Datasheet - Page 225
![80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4682-I/ML
Manufacturer Part Number
PIC18LF4682-I/ML
Description
80KB Flash, 3KB RAM, ECAN, 1024 EEPROM 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4682-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
80KB (40K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 225 of 484
- Download datasheet (9Mb)
FIGURE 17-27:
FIGURE 17-28:
© 2009 Microchip Technology Inc.
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA
SCL
SEN
BCLIF
S
SSPIF
BUS COLLISION DURING START CONDITION (SCL = 0)
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA pulled low by other master.
Reset BRG and assert SDA.
‘0’
‘0’
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
Less than T
BRG
SDA = 0, SCL = 1
PIC18F2682/2685/4682/4685
SDA = 0, SCL = 1
SDA = 0, SCL = 1,
Set SEN, enable START
sequence if SDA = 1, SCL = 1
T
BRG
S
Set S
set SSPIF
T
BRG
T
BRG
Set SSPIF
SCL pulled low after BRG
time-out
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
Interrupt cleared
in software
Interrupts cleared
in software
‘0’
‘0’
‘0’
DS39761C-page 225
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