PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet - Page 279

• Manufacturer Part Number: PIC18LF4221-I/ML
• Description: 4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4221-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25.0
PIC18F2221/2321/4221/4321 family devices incorpo-
rate the standard set of 75 PIC18 core instructions, as
well as an extended set of 8 new instructions for the
optimization of code that is recursive or that utilizes a
software stack. The extended set is discussed later in
this section.
25.1
The standard PIC18 instruction set adds many
enhancements to the previous PIC
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the
operation is to be placed. If ‘d’ is zero, the result is
placed in the WREG register. If ‘d’ is one, the result is
placed in the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
© 2009 Microchip Technology Inc.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)
INSTRUCTION SET SUMMARY
Standard Instruction Set
PIC18F2221/2321/4221/4321 FAMILY
®
MCU instruction
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
• The mode of the table read and table write
• No operand required
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 25-1 shows the general formats that the
instructions can have. All examples use the convention
‘nnh’ to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip MPASM™ Assembler.
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
(specified by ‘k’)
into (specified by ‘f’)
(specified by ‘—’)
(specified by ‘s’)
instructions (specified by ‘m’)
(specified by ‘—’)
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