PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet - Page 270

• Manufacturer Part Number: PIC18LF4221-I/ML
• Description: 4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4221-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2221/2321/4221/4321 FAMILY
REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 24-2:
DS39689F-page 270
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1:
Name
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled
and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
bit 7-1
bit 0
IPEN
Bit 7
—
SUMMARY OF WATCHDOG TIMER REGISTERS
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
SBOREN
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
U-0
—
Bit 6
—
(1)
U-0
—
Bit 5
—
—
U-0
—
Bit 4
RI
—
U-0
—
Bit 3
TO
—
W = Writable bit
-n = Value at POR
U-0
—
Bit 2
PD
—
(1)
U-0
Bit 1
POR
—
—
© 2009 Microchip Technology Inc.
SWDTEN
U-0
—
Bit 0
BOR
SWDTEN
R/W-0
on page
Values
Reset
56
56
bit 0
(1)