PIC18F8722T-I/PT Microchip Technology, PIC18F8722T-I/PT Datasheet - Page 362

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PIC18F8722T-I/PT

Manufacturer Part Number
PIC18F8722T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8722T-I/PT

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F8722T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC18F8722T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC18F8722T-I/PT
Quantity:
1 200
PIC18F8722 FAMILY
TBLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
DS39646C-page 360
Table Write
TBLWT ( *; *+; *-; +*)
None
if TBLWT*,
(TABLAT) → Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register
None
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 5.0 “Memory
Organization” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
1
2
operation
Decode
TBLPTR<0> = 0:Least Significant Byte of
TBLPTR<0> = 1:Most Significant Byte of
0000
Q1
No
operation
operation
TABLAT)
(Read
0000
Q2
No
No
Program Memory Word
Program Memory Word
operation
operation
0000
Q3
No
No
nn=0 *
operation
operation
Register)
(Write to
Holding
=1 *+
=2 *-
=3 +*
11nn
Q4
No
No
TBLWT
Example 1:
Example 2:
Before Instruction
After Instructions (table write completion)
Before Instruction
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
Table Write (Continued)
TBLWT
TBLWT
© 2008 Microchip Technology Inc.
*+;
+*;
=
=
=
=
=
=
=
=
=
=
=
=
=
=
55h
00A356h
FFh
55h
00A357h
55h
34h
01389Ah
FFh
FFh
34h
01389Bh
FFh
34h

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