PIC18F8722T-I/PT Microchip Technology, PIC18F8722T-I/PT Datasheet - Page 343

• Manufacturer Part Number: PIC18F8722T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8722T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
If CNT
Q1
Q1
Q1
PC =
PC =
=
=
=
≠
register ‘f’
operation
operation
operation
Decrement f, Skip if 0
DECFSZ f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest,
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
by a 2-word instruction.
11da
operation
operation
operation
DECFSZ
GOTO
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
PIC18F8722 FAMILY
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Decrement f, Skip if not 0
DCFSNZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest,
skip if result ≠ 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
3 cycles if skip and followed
by a 2-word instruction.
=
=
=
=
≠
=
DCFSNZ
:
:
f {,d {,a}}
11da
operation
operation
operation
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
Process
Data
No
No
No
Q3
Q3
Q3
DS39646C-page 341
TEMP, 1, 0
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff