PIC18F8722T-I/PT Microchip Technology, PIC18F8722T-I/PT Datasheet - Page 306

• Manufacturer Part Number: PIC18F8722T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8722T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
REGISTER 25-6:
DS39646C-page 304
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DEBUG
R/P-1
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ<1:0>: Boot Block Size Select bits
11 = 4K words (8 Kbytes) boot block size
10 = 4K words (8 Kbytes) boot block size
01 = 2K words (4 Kbytes) boot block size
00 = 1K word (2 Kbytes) boot block size
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
XINST
R/P-0
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
W = Writable bit
‘1’ = Bit is set
BBSIZ1
R/P-0
BBSIZ0
R/P-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
R/P-1
LVP
© 2008 Microchip Technology Inc.
x = Bit is unknown
U-0
—
STVREN
R/P-1
bit 0