PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet - Page 255

• Manufacturer Part Number: PIC18F64J90-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.5.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG1 register; if the RC1IE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA1
RCREG1
TXSTA1
BAUDCON1 ABDOVF
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Name
EUSART SYNCHRONOUS SLAVE
RECEPTION
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
—
—
—
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
RXDTP
RC1IE
RC1IP
RC1IF
SREN
TXEN
Bit 5
TXCKP
INT0IE
TX1IE
TX1IP
CREN
SYNC
TX1IF
Bit 4
PIC18F85J90 FAMILY
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RC1IE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RC1IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC1IE, was set.
Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG1 register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
BRGH
FERR
Bit 2
—
—
—
—
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
DS39770C-page 255
RBIF
Bit 0
on Page
Values
Reset
57
60
60
60
59
59
59
61
61
59