PIC18F1330T-I/SO Microchip Technology, PIC18F1330T-I/SO Datasheet - Page 238

8KB, Flash, 256bytes-RAM, 16I/O, 8-bit Family,nanoWatt,MotorControl 18 SOIC .300

PIC18F1330T-I/SO

Manufacturer Part Number
PIC18F1330T-I/SO
Description
8KB, Flash, 256bytes-RAM, 16I/O, 8-bit Family,nanoWatt,MotorControl 18 SOIC .300
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F1330T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F1330T-I/SOTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F1330T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F1230/1330
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39758D-page 238
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR Literal with W
IORLW k
0  k  255
(W) .OR. k  W
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
1
1
IORLW
literal ‘k’
Read
0000
Q2
9Ah
BFh
1001
35h
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0  f  255
d  [0,1]
a  [0,1]
(W) .OR. (f)  dest
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 22.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
 2009 Microchip Technology Inc.
RESULT, 0, 1
f {,d {,a}}
00da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff

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