PIC18F1330T-I/SO Microchip Technology, PIC18F1330T-I/SO Datasheet - Page 200

8KB, Flash, 256bytes-RAM, 16I/O, 8-bit Family,nanoWatt,MotorControl 18 SOIC .300

PIC18F1330T-I/SO

Manufacturer Part Number
PIC18F1330T-I/SO
Description
8KB, Flash, 256bytes-RAM, 16I/O, 8-bit Family,nanoWatt,MotorControl 18 SOIC .300
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F1330T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F1330T-I/SOTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F1330T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F1230/1330
REGISTER 20-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
REGISTER 20-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
DS39758D-page 200
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-0
Note 1:
U-0
U-0
It is recommended to enable the corresponding CPx bit to protect block from external read operations.
It is recommended to enable the corresponding CPx bit to protect block from external read operations.
Unimplemented: Read as ‘0’
EBTR1: Table Read Protection bit (Block 1 Code Memory Area)
1 = Block 1 is not protected from table reads executed in other blocks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0: Table Read Protection bit (Block 0 Code Memory Area)
1 = Block 0 is not protected from table reads executed in other blocks
0 = Block 0 is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB: Table Read Protection bit (Boot Block Memory Area)
1 = Boot Block is not protected from table reads executed in other blocks
0 = Boot Block is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB
R/C-1
U-0
(1)
C = Clearable bit
C = Clearable bit
U-0
U-0
U-0
U-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
U-0
U-0
U-0
 2009 Microchip Technology Inc.
EBTR1
R/C-1
U-0
(1)
EBTR0
R/C-1
U-0
bit 0
bit 0
(1)

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