PIC16LC73A-04I/SO Microchip Technology, PIC16LC73A-04I/SO Datasheet - Page 91

• Manufacturer Part Number: PIC16LC73A-04I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16LC73A-04I/SOR; PIC16LC73A-04I/SOR

Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
FIGURE 11-21: COMBINED FORMAT
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
A master reads a slave immediately after the first byte.
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
(write)
(read)
R/W A
data to this slave and reads data from this slave.
(n bytes - acknowledge)
(n bytes - acknowledge)
Slave Address
Second byte
data transferred
data transferred
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr = repeated
Start Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(n bytes + acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
72 73 73A 74 74A 76 77
Data
Applicable Devices
A
(write)
Data A/A
For 10-bit address:
S
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
For 10-bit address:
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
A master transmitter addresses a slave receiver
with a 10-bit address.
First 7 bits
Sr Slave Address
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr
Slave Address
(write)
Data A
First 7 bits
First 7 bits
(write)
P
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
Second byte
Second byte
A/A
PIC16C7X
P
Data A
DS30390E-page 91
A2
A2
Data
Data
A
A P
P