PIC16LC73A-04I/SO Microchip Technology, PIC16LC73A-04I/SO Datasheet - Page 156

• Manufacturer Part Number: PIC16LC73A-04I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16LC73A-04I/SOR; PIC16LC73A-04I/SOR

PIC16C7X
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
DS30390E-page 156
Inclusive OR W with f
[ label ]
0
d
(W) .OR. (f)
Z
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
1
1
Before Instruction
After Instruction
Move f
[ label ]
0
d
(f)
Z
The contents of register f is moved to a
destination dependant upon the status
of d. If d = 0, destination is W register. If
d = 1, the destination is file register f
itself. d = 1 is useful to test a file regis-
ter since status flag Z is affected.
1
1
After Instruction
Decode
IORWF
Decode
MOVF
Q1
Q1
00
00
f
f
[0,1]
[0,1]
(destination)
127
127
RESULT =
W
RESULT =
W
Z
W = value in FSR register
Z = 1
IORWF
MOVF f,d
register
register
0100
1000
FSR, 0
Read
Read
Q2
Q2
'f'
'f'
(destination)
RESULT, 0
=
=
=
Process
Process
dfff
dfff
f,d
data
data
Q3
Q3
0x13
0x91
0x13
0x93
1
destination
destination
ffff
ffff
Write to
Write to
Q4
Q4
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Move Literal to W
[ label ]
0
k
The eight bit literal 'k' is loaded into W
register
as 0’s.
1
1
After Instruction
Move W to f
[ label ]
0
(W)
Move data from W register to register
'f'
1
1
Before Instruction
After Instruction
None
None
.
MOVLW
MOVWF
Decode
Decode
Q1
Q1
11
00
k
f
(W)
.
1997 Microchip Technology Inc.
127
(f)
255
The don’t cares will assemble
W
OPTION =
W
OPTION =
W
MOVLW k
MOVWF
literal 'k'
register
00xx
0000
0x5A
Read
Read
OPTION_REG
Q2
Q2
'f'
=
0x5A
=
=
kkkk
Process
1fff
Process
data
data
Q3
Q3
f
0xFF
0x4F
0x4F
0x4F
register 'f'
Write to
kkkk
ffff
Write
Q4
Q4
W