PIC16LC73A-04I/SO Microchip Technology, PIC16LC73A-04I/SO Datasheet - Page 59

• Manufacturer Part Number: PIC16LC73A-04I/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04I/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16LC73A-04I/SOR; PIC16LC73A-04I/SOR

7.0
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
FIGURE 7-1:
FIGURE 7-2:
1997 Microchip Technology Inc.
RA4/T0CKI
pin
Instruction
TMR0
PC
(Program
Counter)
Fetch
Instruction
Executed
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
TIMER0 MODULE
Applicable Devices
72 73 73A 74 74A 76 77
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
T0SE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
F
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
OSC
PC-1
/4
MOVWF TMR0
T0+1
T0CS
PC
0
1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PS2, PS1, PS0
T0+2
Write TMR0
executed
Programmable
PC+1
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
Source Edge Select bit T0SE (OPTION<4>). Clearing
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
7.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
PSout
Read TMR0
reads NT0
NT0
PC+3
(2 cycle delay)
Sync with
Timer0 Interrupt
Applicable Devices
72 73 73A 74 74A 76 77
Internal
clocks
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
PSout
MOVF TMR0,W
Read TMR0
reads NT0 + 1
NT0+1
PIC16C7X
Data bus
TMR0
PC+5
8
DS30390E-page 59
Set interrupt
Read TMR0
reads NT0 + 2
flag bit T0IF
on overflow
NT0+2
PC+6
T0