PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 341

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
1997 Microchip Technology Inc.
Name
USART Baud Rate Generator (BRG)
Baud Rate Generator Register
CSRC
SPEN
Bit 7
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedi-
cated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit
timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous
mode bit BRGH is ignored.
different USART modes which only apply in master mode (internal clock).
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be
calculated using the formula in
255). From this, the error in baud rate can be determined.
Table 18-1: Baud Rate Formula
Example 18-1
Example 18-1:
It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This
is because the F
Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
Table 18-2: Registers Associated with Baud Rate Generator
X = value in SPBRG (0 to 255)
Bit 6
RX9
TX9
Desired Baud rate
Calculated Baud Rate =
Error
SYNC
F
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
0
1
OSC
SREN
TXEN
Bit 5
= 16 MHz
9600
X
(Asynchronous) Baud Rate = F
shows the calculation of the baud rate error for the following conditions:
(Synchronous) Baud Rate = F
OSC
Calculating Baud Rate Error
CREN
SYNC
Bit 4
/ (16(X + 1)) equation can reduce the baud rate error in some cases.
=
=
=
=
=
=
=
BRGH = 0 (Low Speed)
Bit 3
Table 18-1
Fosc / (64 (X + 1))
16000000 / (64 (X + 1))
16000000 / (64 (25 + 1))
9615
(Calculated Baud Rate - Desired Baud Rate)
(9615 - 9600) / 9600
0.16%
25.042 = 25
—
—
Table
BRGH
FERR
18-1, where X equals the value in the SPBRG register (0 to
Bit 2
shows the formula for computation of the baud rate for
Desired Baud Rate
Section 18. USART
OSC
OSC
OERR
TRMT
Bit 1
/(64(X+1))
/(4(X+1))
RX9D
TX9D
Bit 0
Baud Rate= F
0000 -010
0000 -00x
0000 0000
Value on:
BRGH = 1 (High Speed)
POR,
BOR
DS31018A-page 18-5
NA
OSC
other resets
Value on all
0000 -010
0000 -00x
0000 0000
/(16(X+1))
18