PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 173

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4
1997 Microchip Technology Inc.
GIE bit
INSTRUCTION
FLOW
T0IF bit
Instruction
fetched
Instruction
executed
Timer0
CLKOUT(3)
OSC1
PC
TMR0 Interrupt
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
Q1
2: Interrupt latency = 4T
3: CLKOUT is available only in RC oscillator mode.
FEh
Inst (PC)
Inst (PC-1)
Q2
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This
overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE
(INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service rou-
tine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP. See
Figure 11-4: TMR0 Interrupt Timing
1
PC
Q3
Q4
CY
Q1
FFh
where T
Inst (PC+1)
Inst (PC)
Q2
1
PC +1
CY
Q3
= instruction cycle time.
Q4
Q1
00h
Dummy cycle
Q2
PC +1
Q3
Section 11. Timer0
Q4
Figure 11-4
Q1
01h
Dummy cycle
Inst (0004h)
Q2
0004h
Q3
for Timer0 interrupt timing.
Q4
Q1
DS31011A-page 11-5
02h
Inst (0004h)
Inst (0005h)
Q2
0005h
Q3
Q4
11