PIC16F72-E/SP Microchip Technology, PIC16F72-E/SP Datasheet - Page 72
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PIC16F72-E/SP
Manufacturer Part Number
PIC16F72-E/SP
Description
28 PIN, 3.5KB STD FLASH, 128 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
Specifications of PIC16F72-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC16F72
11.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator that does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer Wake-up). The TO bit in the STATUS register will
be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (see Section 11.1).
FIGURE 11-11:
TABLE 11-7:
DS39597C-page 70
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
Address
Note: PSA and PS2:PS0 are bits in the OPTION register.
Config. bits
OPTION
Name
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable Bit
WATCHDOG TIMER BLOCK DIAGRAM
WDT
From TMR0 Clock Source
(Figure 4-1)
RBPU
Bit 7
(1)
BOREN
INTEDG
Bit 6
0
1
PSA
(1)
M
U
X
T0CS
Bit 5
—
T0SE
0
Bit 4
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION register.
CP
Time-out
8 - to - 1 MUX
MUX
Note 1: The CLRWDT and SLEEP instructions
WDT
Postscaler
PWRTEN
2: When a CLRWDT instruction is executed
1
8
Bit 3
PSA
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
(1)
PSA
To TMR0 (Figure 4-1)
WDTEN
Bit 2
PS2
© 2007 Microchip Technology Inc.
PS2:PS0
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0