PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 11

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

1.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 1-2.
FIGURE 1-2:
EXAMPLE 1-1:
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @ address SUB_1
2001 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction
Cycle
(RC mode)
SUB_1
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
Q1
INSTRUCTION PIPELINE FLOW
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Preliminary
Execute INST (PC)
Fetch INST (PC+1)
Q2
Execute 2
Fetch 3
PC+1
T
CY
1.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 1-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3,
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
2
Q3
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
T
CY
3
Q1
PIC16C925/926
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
T
PC+2
CY
4
Q3
Q4
DS39544A-page 9
T
CY
Internal
Phase
Clock
5