KS8995X Micrel Inc, KS8995X Datasheet - Page 4

• Manufacturer Part Number: KS8995X
• Description: Special Function IC
• Manufacturer: Micrel Inc

Specifications of KS8995X

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 576-1021 - BOARD EVAL EXPERIMENT KS8995X
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

KS8995X
Table of Contents
M9999-120403
System Level Applications .............................................................................................................................................................. 6
Pin Description (by Number) ........................................................................................................................................................... 8
Pin Description (by Name) ............................................................................................................................................................ 13
Pin Configuration ........................................................................................................................................................................... 18
Introduction
Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19
Functional Overview: Switch Core ............................................................................................................................................... 21
MII Interface Operation .................................................................................................................................................................. 23
SNI Interface Operation ................................................................................................................................................................. 25
Advanced Functionality ................................................................................................................................................................. 25
MII Management Interface (MIIM) .................................................................................................................................................. 28
Register Map
100BaseTX Transmit ............................................................................................................................................................... 19
100BaseTX Receive ................................................................................................................................................................ 19
PLL Clock Synthesizer ............................................................................................................................................................ 19
Scrambler/De-scrambler (100BaseTX only) ............................................................................................................................ 19
100BaseFX Operation ............................................................................................................................................................. 19
100BaseFX Signal Detection ................................................................................................................................................... 20
100BaseFX Far End Fault ....................................................................................................................................................... 20
10BaseT Transmit ................................................................................................................................................................... 20
10BaseT Receive .................................................................................................................................................................... 20
Power Management ................................................................................................................................................................ 20
MDI/MDI-X Auto Crossover ..................................................................................................................................................... 20
Auto-Negotiation ...................................................................................................................................................................... 20
Address Look Up ..................................................................................................................................................................... 21
Learning
Migration
Aging
Switching Engine ..................................................................................................................................................................... 21
MAC (Media Access Controller) Operation ............................................................................................................................. 22
QoS Support ............................................................................................................................................................................ 25
Rate Limit Support ................................................................................................................................................................... 27
Configuration Interface ............................................................................................................................................................ 28
Global Registers ...................................................................................................................................................................... 29
Inter-Packet Gap ............................................................................................................................................................. 22
Backoff Algorithm ............................................................................................................................................................ 22
Late Collision .................................................................................................................................................................. 22
Illegal Frame ................................................................................................................................................................... 22
Flow Control .................................................................................................................................................................... 22
Half-Duplex Back Pressure ............................................................................................................................................. 22
Broadcast Storm Protection ............................................................................................................................................ 23
I2C Master Serial Bus Configuration ............................................................................................................................... 28
Register 0 (0x00): Chip ID0 ............................................................................................................................................ 29
Register 1 (0x01): Chip ID1/Start Switch ....................................................................................................................... 29
Register 2 (0x02): Global Control 0 ................................................................................................................................ 29
Register 3 (0x03): Global Control 1 ................................................................................................................................ 30
Register 4 (0x04): Global Control 2 ................................................................................................................................ 31
Register 5 (0x05): Global Control 3 ................................................................................................................................ 31
Register 6 (0x06): Global Control 4 ................................................................................................................................ 32
Register 7 (0x07): Global Control 5 ................................................................................................................................ 32
............................................................................................................................................................................ 19
............................................................................................................................................................................ 21
............................................................................................................................................................................ 21
............................................................................................................................................................................ 21
............................................................................................................................................................................ 29
4
December 2003
Micrel