DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F5015-20I/PT
• Description: Digital Signal Processor
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501520IPT

4. Module: QEI
© 2010 Microchip Technology Inc.
The Index Pulse Reset mode of the Quadrature
Encoder Interface (QEI) does not work properly
when used along with count error detection. When
counting upwards, the POSCNT register will incre-
ment one extra count after the index pulse is
received. The extra count will generate a false
count error interrupt.
Work around
There are multiple work arounds for this issue,
depending on the specific requirements of the
application:
1. Ignore count error interrupts when the counting
2. The user may disable count error interrupts by
3. The user may disable the index pulse reset
Affected Silicon Revisions
A0
X
direction is upwards and the POSCNT register
has the value of MAXCNT + 1.
setting the CEID bit in the DFLTCON register.
feature
(QEICON<2>). Writing QEICON = 0x0600 will
provide a QEI interrupt each time an index
pulse is received, but the POSCNT register will
not be modified. The POSCNT register value
can be read in the QEI interrupt handler and
used as an offset value to calculate the
absolute position of the encoder disc with
respect to the index pulse.
by
clearing
the
POSRES
bit
5. Module: ADC
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero. This means that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> TO ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
A0
X
dsPIC30F5015/5016
DS80452C-page 5