DSPIC30F5015-20I/PT Microchip Technology, DSPIC30F5015-20I/PT Datasheet - Page 13

Digital Signal Processor

DSPIC30F5015-20I/PT

Manufacturer Part Number
DSPIC30F5015-20I/PT
Description
Digital Signal Processor
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F5015-20I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F501520IPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F5015-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
19. Module: CAN
20. Module: QEI
21. Module: QEI
© 2010 Microchip Technology Inc.
CAN Receive filters 3, 4 and 5 may not work for a
given combination of instruction cycle speed and
CAN bit time quanta.
Work around
Do not use CAN RX filters 3, 4 and 5. Instead, use
filters 0, 1 and 2.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt
should be generated after an input pulse on the
QEA input. This interrupt is not generated in the
affected silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the QEIx-
CON register are set, the POSCNT counter
should not increment but erroneously does, and
if allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while running the QEI in Timer Gated Accumulation
mode, initialize MAXCNT = 0.
Affected Silicon Revisions
A0
A0
A0
X
X
X
22. Module: ADC
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding
(PMDx) register, prior to executing a PWRSAV
#0 instruction.
Affected Silicon Revisions
A0
X
dsPIC30F5015/5016
PD
) may exceed the specifications listed
Peripheral
Module
PD
DS80452C-page 13
specifications
Disable

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