DSPIC30F4011T-30I/PT Microchip Technology, DSPIC30F4011T-30I/PT Datasheet - Page 88
![IC,DSP,16-BIT,CMOS,TQFP,44PIN,PLASTIC](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC30F4011T-30I/PT
Manufacturer Part Number
DSPIC30F4011T-30I/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F4012-30ISO.pdf
(238 pages)
2.DSPIC30F4012-30ISO.pdf
(18 pages)
3.DSPIC30F4012-30ISO.pdf
(6 pages)
4.DSPIC30F4012-30ISO.pdf
(16 pages)
5.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4011T-30I/PT
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F4011T30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4011T-30I/PT
Manufacturer:
ST
Quantity:
2 001
Company:
Part Number:
DSPIC30F4011T-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F4012-30ISO PDF datasheet
- DSPIC30F4012-30ISO PDF datasheet #2
- DSPIC30F4012-30ISO PDF datasheet #3
- DSPIC30F4012-30ISO PDF datasheet #4
- DSPIC30F4012-30ISO PDF datasheet #5
- Current page: 88 of 238
- Download datasheet (4Mb)
dsPIC30F4011/4012
13.5
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
13.6
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
DS70135G-page 88
Output Compare Operation During
CPU Sleep Mode
Output Compare Operation During
CPU Idle Mode
13.7
The output compare channels have the ability to gener-
ate an interrupt on a compare match for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated if enabled.
The OCxIF bit is located in the corresponding IFSx reg-
ister, and must be cleared in software. The interrupt is
enabled via the respective Compare Interrupt Enable
(OCxIE) bit, located in the corresponding IECx register.
For the PWM mode, when an event occurs, the respec-
tive Timer Interrupt Flag (T2IF or T3IF) is asserted and
an interrupt will be generated if enabled. The TxIF bit is
located in the IFS0 register and must be cleared in
software. The interrupt is enabled via the respective
Timer Interrupt Enable bit (T2IE or T3IE) located in the
IEC0 register. The output compare interrupt flag is
never set during the PWM mode of operation.
Output Compare Interrupts
© 2010 Microchip Technology Inc.
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