DSPIC30F4011T-30I/PT Microchip Technology, DSPIC30F4011T-30I/PT Datasheet - Page 111

IC,DSP,16-BIT,CMOS,TQFP,44PIN,PLASTIC

DSPIC30F4011T-30I/PT

Manufacturer Part Number
DSPIC30F4011T-30I/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4011T-30I/PT

Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F4011T30IP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4011T-30I/PT
Manufacturer:
ST
Quantity:
2 001
Part Number:
DSPIC30F4011T-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
16.3
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDO1 pin is driven. When SS1 pin goes high, the
SDO1 pin is no longer driven. Also, the SPI module is
resynchronized and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb,
even if SS1 had been deasserted in the middle of a
transmit/receive.
© 2010 Microchip Technology Inc.
Slave Select Synchronization
16.4
During Sleep mode, the SPI module is shut down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
dsPIC30F4011/4012
SPI Operation During CPU Sleep
Mode
SPI Operation During CPU Idle
Mode
DS70135G-page 111

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