DSPIC30F2011T-20E/SO Microchip Technology, DSPIC30F2011T-20E/SO Datasheet - Page 80
![IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC](/photos/6/76/67656/150-18-soic_sml.jpg)
DSPIC30F2011T-20E/SO
Manufacturer Part Number
DSPIC30F2011T-20E/SO
Description
IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011T-20E/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20IP PDF datasheet #6
- Current page: 80 of 210
- Download datasheet (3Mb)
dsPIC30F2011/2012/3012/3013
10.1
The 32-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal T
to increment the respective timer when the gate input
signal (T2CK pin) is asserted high. Control bit, TGATE
(T2CON<6>), must be set to enable this mode. When
in this mode, Timer2 is the originating clock source.
The TGATE setting is ignored for Timer3. The timer
must be enabled (TON = 1) and the timer clock source
set to internal (TCS = 0).
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
When a match occurs between the 32-bit timer
(TMR3/TMR2) and the 32-bit combined period register
(PR3/PR2), or between the 16-bit timer TMR3 and the
16-bit period register PR3, a special ADC trigger event
signal is generated by Timer3.
10.3
The input clock (F
has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits, TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler
operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• A write to the TMR2/TMR3 register
• A write to the T2CON/T3CON register
• A device Reset, such as a POR and BOR
However, if the timer is disabled (TON = 0), the Timer
2 prescaler cannot be reset since the prescaler clock is
halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70139G-page 80
Timer Gate Operation
ADC Event Trigger
Timer Prescaler
OSC
/4 or external clock) to the timer
CY
10.4
The timer does not operate during CPU Sleep mode
because the internal clocks are disabled.
10.5
The
interrupt-on-period match or on the falling edge of the
external gate signal. When the 32-bit timer count
matches the respective 32-bit period register, or the
falling edge of the external “gate” signal is detected, the
T3IF bit (IFS0<7>) is asserted and an interrupt is
generated if enabled. In this mode, the T3IF interrupt
flag is used as the source of the interrupt. The T3IF bit
must be cleared in software.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
32-bit
Timer Operation During Sleep
Mode
Timer Interrupt
timer
module
© 2010 Microchip Technology Inc.
can
generate
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