DSPIC30F2011T-20E/SO Microchip Technology, DSPIC30F2011T-20E/SO Datasheet - Page 117
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DSPIC30F2011T-20E/SO
Manufacturer Part Number
DSPIC30F2011T-20E/SO
Description
IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011T-20E/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20IP PDF datasheet #6
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- Download datasheet (3Mb)
The configuration procedures in the next section pro-
vide the required setup values for the conversion
speeds above 100 ksps.
16.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
FIGURE 16-3:
© 2010 Microchip Technology Inc.
the recommended circuit shown in Figure 16-2.
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
(14 + 1) x 200,000
200 KSPS CONFIGURATION
GUIDELINE
Note: C
1
Legend: C
VA
PIN
REF
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
+ and V
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
= 334 ns
PIN
REF
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
- pins following
Table
dsPIC30F2011/2012/3012/3013
AD
V
by
16-1.
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
± 500 nA
IC
≤ 250Ω
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
conjunction with the guidelines described above allows
a conversion speed of 200 ksps. See
code example.
16.8
The analog input model of the 12-bit ADC is shown in
Figure
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the ADC, the
maximum recommended source impedance, R
is 2.5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
SS
) impedance combine to directly affect the time
16-3. The total sampling time for the A/D is a
Sampling
Switch
A/D Acquisition Requirements
impedance
R
SS
IC
PIN
) and the internal sampling switch
R
negligible if Rs ≤ 2.5 kΩ.
SS
V
SS
HOLD
C
= DAC capacitance
= 18 pF
≤ 3 kΩ
HOLD
(R
) must be allowed to fully
S
),
HOLD
the
DS70139G-page 117
Example 16-1
AD
. The combined
selection in
interconnect
for
S
,
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