CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 42

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

14.33 Status Registers
The following Status registers are read-only:
Status Register (04h)
page 35),
tion 14.6 on page 35) and
(13h)
CS61884 generates an interrupt on the INT pin any
time an unmasked status register bit changes.
14.33.1 Interrupt Enable Registers
The Interrupt Enable registers:
able Register (06h)
DFM Interrupt Enable Register (07h)
tion 14.8 on page 36),
ister (14h)
AWG Overflow Interrupt Enable Register
(1Ah)
changes in status register state to cause an interrupt
42
(See Section 14.20 on page 39). The
(See Section 14.27 on page
DFM Status Register (05h)
(See Section 14.21 on page 39) and
(See Section 14.7 on page 36),
AIS Interrupt Enable Reg-
(See Section 14.5 on
AIS Status Register
LOS Interrupt En-
41),
(See Sec-
(See Sec-
enable
LOS
on the INT pin. Interrupts are maskable on a per
channel basis. When an Interrupt Enable register
bit is 0, the corresponding Status register bit is dis-
abled from causing an interrupt on the INT pin.
NOTE: Disabling an interrupt has no effect on the sta-
14.33.2 Interrupt Status Registers
The following interrupt status registers:
terrupt Status Register (08h)
on page 36),
(09h)
rupt Status Register (15h)
page 40) and
Register (1Bh)
dicate a change in status of the corresponding status
registers in host mode. Reading these registers
clears the interrupt, which deactivates the INT pin.
(See Section 14.10 on page 36),
tus reflected in the associated status register.
AWG Overflow Interrupt Status
DFM Interrupt Status Register
(See Section 14.28 on page 41), in-
(See Section 14.22 on
(See Section 14.9
CS61884
AIS Inter-
LOS In-
DS485F1