CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 19

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

3.7 Analog RX/TX Data I/O
DS485F1
RPOS7/RDATA7
RNEG7/BPV7
SYMBOL
SYMBOL
RRING0
RRING1
TRING0
TRING1
RCLK7
RTIP0
RTIP1
TTIP0
TTIP1
LQFP
LQFP
143
142
141
45
46
48
49
52
51
55
54
FBGA
FBGA
M5
M7
N5
N7
A1
A2
A3
P5
P7
L5
L7
TYPE
TYPE
O
O
O
O
O
O
O
I
I
I
I
Receive Clock Output Port 7
Receive Positive Pulse/ Receive Data Output Port 7
Receive Negative Pulse/Bipolar Violation Output Port 7
Transmit Tip Output Port 0
Transmit Ring Output Port 0
TTIP and TRING pins are the differential outputs of the
transmit driver. The driver internally matches impedances
for E1 75 Ω, E1 120 Ω and T1/J1 100 Ω lines requiring only
a 1:2 transformer. The CBLSEL pin is used to select the
appropriate line matching impedance only in “Hardware”
mode. In host mode, the appropriate line matching imped-
ance is selected by the
(See Section 14.18 on page 39).
NOTE: TTIP and TRING are forced to a high impedance state
Receive Tip Input Port 0
Receive Ring Input Port 0
RTIP and RRING are the differential line inputs to the re-
ceiver. The receiver uses either Internal Line Impedance or
External Line Impedance modes to match the line imped-
ances for E1 75Ω, E1 120Ω or T1/J1 100Ω modes.
Internal Line Impedance Mode - The receiver uses the
same external resistors to match the line impedance (Refer
to
External Line Impedance Mode - The receiver uses differ-
ent external resistors to match the line impedance (Refer to
Figure 18 on page
- In host mode, the appropriate line impedance is selected
by the
14.18 on page 39).
- In hardware mode, the CBLSEL pin in combination with
the LEN pins select the appropriate line impedance. (Refer
to
NOTE: Data and clock recovered from the signal input on
Transmit Tip Output Port 1
Transmit Ring Output Port 1
Receive Tip Input Port 1
Receive Ring Input Port 1
Figure 17 on page
Table 3 on page 15
Line Length Data Register (11h)
when the TCLK pin is “Low” for over 12µS or the
TXOE pin is forced “Low”.
these pins are output via RCLK, RPOS, and RNEG.
52).
51).
DESCRIPTION
DESCRIPTION
for proper line impedance settings).
Line Length Data Register (11h)
(See Section
CS61884
19