CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 17

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

DS485F1
RPOS0/RDATA0
RPOS1/RDATA1
TPOS1/TDATA1
TPOS2/TDATA2
RNEG0/BPV0
TNEG1/UBS1
RNEG1/BPV1
TNEG2/UBS2
SYMBOL
RCLK0
RCLK1
TCLK1
TCLK2
LQFP
39
40
41
29
30
31
32
33
34
81
80
79
FBGA
L14
L13
L12
M1
M2
M3
P1
P2
P3
L1
L2
L3
TYPE
O
O
O
O
O
O
I
I
I
I
I
I
Receive Clock Output Port 0
- When MCLK is active, this pin outputs the recovered clock
from the signal input on RTIP and RRING. In the event of
LOS, the RCLK output transitions from the recovered clock
to MCLK.
- If MCLK is held “High”, the clock recovery circuitry is dis-
abled and the RCLK output is driven by the XOR of RNEG
and RPOS.
- If MCLK is held “Low”, this output is in a high-impedance
state.
Receive Positive Pulse/ Receive Data Output Port 0
Receive Negative Pulse/Bipolar Violation Output Port 0
The function of the RPOS/RDATA and RNEG/BPV outputs
are determined by whether Unipolar, Bipolar, or RZ input
mode has been selected. During LOS, the RPOS/RNEG
outputs will remain active.
NOTE: The RPOS/RNEG outputs can be High-Z by holding
Bipolar Output Mode - When configured for Bipolar opera-
tion, NRZ Data is recovered from RTIP/RRING and output
on RPOS/RNEG. A high signal on RPOS or RNEG corre-
spond to the receipt of a positive or negative pulse on
RTIP/RRING respectively. The RPOS/RNEG outputs are
valid on the falling or rising edge of RCLK as configured by
CLKE.
Unipolar Output Mode - When unipolar mode is activated,
the recovered data is output on RDATA. The decoder sig-
nals bipolar Violations on the RNEG/BPV pin.
RZ Output Mode - In this mode, the RPOS/RNEG pins
output RZ data recovered by slicing the signal present on
RTIP/RRING. A positive pulse on RTIP with respect to
RRING generates a logic 1 on RPOS; a positive pulse on
RRING with respect to RTIP generates a logic 1 on RNEG.
The polarity of the output on RPOS/RNEG is selectable us-
ing the CLKE pin. In this mode, external circuitry is used to
recover clock from the received signal.
Transmit Clock Input Port 1
Transmit Positive Pulse/Transmit Data Input Port 1
Transmit Negative Pulse/Unipolar-Bipolar Select Port 1
Receive Clock Output Port 1
Receive Positive Pulse/ Receive Data Output Port 1
Receive Negative Pulse/Bipolar Violation Output Port 1
Transmit Clock Input Port 2
Transmit Positive Pulse/Transmit Data Input Port 2
Transmit Negative Pulse/Unipolar-Bipolar Select Port 2
MCLK Low.
DESCRIPTION
CS61884
17