CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 33

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

transferred at a rate of up to 400 Kbits/sec in fast
mode. The number of interfaces to the bus is solely
dependent on the limiting bus capacitance of 400
pF. When 8-bit parallel interface operation is being
used, SDA and SCL can be tied directly to ground.
The I
mable via the I2C_ADR Register (0×0F). When
I
must be tied to ground. PDAT [7:0] are available to
be used for GPIO operation in I
mode. For 3.3 V operation it is necessary to have
the appropriate level shifting for I
8.1.2. 8-bit Parallel Interface
The CS4954/5 is equipped with a full 8-bit parallel
microprocessor write and read control port. Along
with the PDAT [7:0] pins, the control port interface
is comprised of host read (RD) and host write (WR)
DS278PP4
2
C interface operation is being used, RD and WR
2
C bus address for the CS4954/5 is program-
PDAT[7:0]
ADDR
WR
RD
RD
Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle
2
2
C host interface
C signals.
T
T
as
rec
T
rda
T
rpw
active low strobes and host address enable
(ADDR), which, when low, enables unique address
register accesses. The control port is used to access
internal registers which configure the CS4954/5 for
various modes of operation. The internal registers
are uniquely addressed via an address register. The
address register is accessed during a host write cy-
cle with the WR and ADDR pins set low. Host
write cycles with ADDR set high will write the 8-
bits on the PDAT [7:0] pins into the register cur-
rently selected by the address register. Likewise
read cycles occur with RD set low and ADDR set
high will return the register contents selected by the
address register. Reference the detailed electrical
timing parameter section of this data sheet for exact
host parallel interface timing characteristics and
specifications.
T
rd
T
rah
T
rdh
T
rec
CS4954 CS4955
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